Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits

The intrinsic atomistic variability of nano-scale integrated circuit (IC) technology must be taken into account when analyzing circuit designs to predict likely yield. Monte Carlo (MC) based statistical techniques aim to do this by analysing many randomized copies of the circuit. A major problem is the computational cost of carrying out sufficient analyses to produce statistically reliable results. The MC analyses required for asynchronous circuits are more difficult than are generally required for clocked circuits because of the more complex timing patterns created by handshaking mechanisms. It is important to reduce the computational complexity of MC analysis required for asynchronous circuits. The use of 'Statistical Behavioural Circuit Blocks (SBCB)' is investigated as a means of reducing the dimensionality of the analysis, and this is combined with an implementation of 'Statistical Blockade' to achieve significant reduction in the computational costs. The reduction in computation time achieved by the more efficient MC analysis is illustrated by statistically analysing several simple handshaking circuits. © 2010 IEEE.