Contactless Heterogeneous 3-D ICs for Smart Sensing Systems

Ioannis Papistas, Vasileios Pavlidis

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A heterogeneous contactless transceiver circuit is designed to provide inter-tier signalling for a 3-D system considering specific bonding constraints. The system is composed of two tiers, a 65 nm processing tier and a 0.35 μm sensing tier. Face-to-back integration is chosen to support fluidic sensing. Half duplex communication between the tiers is provided through inductive links. Each tier is considered to be fabricated in a different technology to enable low manufacturing cost and benefit from the advantages each technology offers. Both the uplink and downlink transceivers achieve data rates that reach 1 Gbps with non-return-to-zero data encoding. Energy efficiency is the predominant objective, with the uplink dissipating 5.28 pJ/b and 8.67 pJ/b for the downlink. A 6.8× power reduction is demonstrated when using heterogeneous technologies, compared to a state-of-the-art 0.35 μm transceiver, while the dissipated energy is decreased by 37.5% as compared to a state-of-the-art 65 nm transceiver. Process variation analysis is also performed to ensure the proposed circuit operates correctly across several process corners, covering a broad design space. To improve system robustness, an overhead of 2.3% on the peak power and <1% on the average power is shown, respectively.
Original languageEnglish
Number of pages12
JournalIntegration, the VLSI Journal
Early online date10 Apr 2018
Publication statusPublished - 2018


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