Damage related deep electron levels in ion implanted GaAs.

The use of ion implantation in the fabrication of GaAs MESFET integrated circuits is now well established, although closer control of the semi-insulating GaAs substrates and of the wafer processing is essential if good yields are to be achieved. In order to study lattice damage associated with the implantation, various ion implanted, semi-insulating GaAs substrates have been investigated by using a polaron S4700 capacitance DLTS system. It has been found that high temperature annealing in arsenic or arsine overpressures may not completely remove electrically active defects associated with ion implantation in GaAs. An additional low temperature anneal under conditions which permit the in-diffusion of As vacancies has been shown to significantly reduce the concentrations of residual damage related deep states.