Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults

Guangda Zhang, J. Garside, Wei Song, J. Navaridas, Zhiying Wang, Javier Navaridas

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


Asynchronous Networks-on-Chip (NoCs) have been proposed as a promising infrastructure to provide scalable and efficient on-chip communication for many-core systems. Using the Quasi-delay-insensitive (QDI) implementation, asynchronous NoCs could achieve timing-robustness. However, the advancing semiconductor technology leads to shrinking transistor dimensions and increasing chip density, accelerating the occurrence of faults, especially transient faults. Transient faults emerging on QDI circuits could cause not only data errors (symbol corruption and insertion), but also deadlock. When the deadlock happens on asynchronous NoCs, it can spread over the whole network and paralyse its function. This deadlock has not been fully studied while most traditional fault-tolerant techniques cannot deal with it. Using a new model built for QDI pipelines, the formation and behaviour of the deadlock caused by transient faults are systematically studied. Using the summarized deadlock patterns, the fault position can be precisely located and the fault type can be diagnosed. A fine-grained recovery mechanism is proposed to recover the network from different deadlocks. As a design case, an asynchronous NoC is designed which can recover from the deadlock caused by both transient and permanent faults on links. Detailed experimental results are given.
Original languageEnglish
Title of host publicationAsynchronous Circuits and Systems (ASYNC), 2015 21st IEEE International Symposium
Place of PublicationUSA
Number of pages8
ISBN (Print)1522-8681
Publication statusPublished - 4 May 2015
EventAsynchronous Circuits and Systems (ASYNC), 2015 21st IEEE International Symposium on - Mountain View, CA
Duration: 4 May 20156 May 2015


ConferenceAsynchronous Circuits and Systems (ASYNC), 2015 21st IEEE International Symposium on
CityMountain View, CA


  • asynchronous circuits;fault diagnosis;network-on-chip;system recovery;QDI implementation;QDI pipelines;asynchronous NoC;asynchronous networks-on-chip;chip density;data errors;deadlock patterns;fault position;fine-grained recovery mechanism;many-core systems;on-chip communication;quasi-delay-insensitive implementation;semiconductor technology;shrinking transistor dimensions;timing-robustness;transient faults;Circuit faults;Latches;Pipelines;Silicon;System recovery;Transient analysis;Wires;asynchronous;deadlock;fault tolerance;network-on-chip;quasi-delay-insensitive;transient


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