Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

W. J. Bainbridge; S. B. Furber

doi:10.1109/ASYNC.2001.914075

Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

W. J. Bainbridge, S. B. Furber

Advanced Processor Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution

Abstract

The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied through the use of a shared bus. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in much greater area requirements and still suffers from some of the same problems. This paper introduces a delay-insensitive, asynchronous approach to interconnect over long paths using 1-of-4 encoded channels switched through multiplexers. A re-implementation of the MARBLE SoC bus (as used in the AMULET3H chip) using this technique shows that it can provide a higher throughput than the simpler tristate bus while using a narrower datapath. © 2001 IEEE.

Original language	English
Title of host publication	Proceedings - International Symposium on Asynchronous Circuits and Systems\|Proc. Int. Symp. Asynchr. Circuits Syst.
Publisher	IEEE Computer Society
Pages	118-126
Number of pages	8
DOIs	https://doi.org/10.1109/ASYNC.2001.914075
Publication status	Published - 2001
Event	7th International Symposium on Asynchronous Circuits and Systems, ASYNC 2001 - Salt Lake City, UT Duration: 1 Jul 2001 → … http://dblp.uni-trier.de/db/conf/async/async2001.html#BainbridgeF01http://dblp.uni-trier.de/rec/bibtex/conf/async/BainbridgeF01.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/async/BainbridgeF01

Conference

Conference	7th International Symposium on Asynchronous Circuits and Systems, ASYNC 2001
City	Salt Lake City, UT
Period	1/07/01 → …
Internet address	http://dblp.uni-trier.de/db/conf/async/async2001.html#BainbridgeF01http://dblp.uni-trier.de/rec/bibtex/conf/async/BainbridgeF01.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/async/BainbridgeF01

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10.1109/ASYNC.2001.914075

Cite this

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title = "Delay insensitive system-on-chip interconnect using 1-of-4 data encoding",

abstract = "The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied through the use of a shared bus. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in much greater area requirements and still suffers from some of the same problems. This paper introduces a delay-insensitive, asynchronous approach to interconnect over long paths using 1-of-4 encoded channels switched through multiplexers. A re-implementation of the MARBLE SoC bus (as used in the AMULET3H chip) using this technique shows that it can provide a higher throughput than the simpler tristate bus while using a narrower datapath. {\textcopyright} 2001 IEEE.",

author = "Bainbridge, \{W. J.\} and Furber, \{S. B.\}",

year = "2001",

doi = "10.1109/ASYNC.2001.914075",

language = "English",

pages = "118--126",

booktitle = "Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.",

publisher = "IEEE Computer Society ",

address = "United States",

note = "7th International Symposium on Asynchronous Circuits and Systems, ASYNC 2001 ; Conference date: 01-07-2001",

url = "http://dblp.uni-trier.de/db/conf/async/async2001.html\#BainbridgeF01http://dblp.uni-trier.de/rec/bibtex/conf/async/BainbridgeF01.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/async/BainbridgeF01",

}

Bainbridge, WJ & Furber, SB 2001, Delay insensitive system-on-chip interconnect using 1-of-4 data encoding. in Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.. IEEE Computer Society , pp. 118-126, 7th International Symposium on Asynchronous Circuits and Systems, ASYNC 2001, Salt Lake City, UT, 1/07/01. https://doi.org/10.1109/ASYNC.2001.914075

TY - GEN

T1 - Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

AU - Bainbridge, W. J.

AU - Furber, S. B.

PY - 2001

Y1 - 2001

N2 - The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied through the use of a shared bus. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in much greater area requirements and still suffers from some of the same problems. This paper introduces a delay-insensitive, asynchronous approach to interconnect over long paths using 1-of-4 encoded channels switched through multiplexers. A re-implementation of the MARBLE SoC bus (as used in the AMULET3H chip) using this technique shows that it can provide a higher throughput than the simpler tristate bus while using a narrower datapath. © 2001 IEEE.

AB - The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied through the use of a shared bus. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in much greater area requirements and still suffers from some of the same problems. This paper introduces a delay-insensitive, asynchronous approach to interconnect over long paths using 1-of-4 encoded channels switched through multiplexers. A re-implementation of the MARBLE SoC bus (as used in the AMULET3H chip) using this technique shows that it can provide a higher throughput than the simpler tristate bus while using a narrower datapath. © 2001 IEEE.

UR - https://www.scopus.com/pages/publications/77957933800

U2 - 10.1109/ASYNC.2001.914075

DO - 10.1109/ASYNC.2001.914075

M3 - Conference contribution

SP - 118

EP - 126

BT - Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.

PB - IEEE Computer Society

T2 - 7th International Symposium on Asynchronous Circuits and Systems, ASYNC 2001

Y2 - 1 July 2001

ER -

Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

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