The design of a processing subsystem for a prototype data-flow computer being built at Manchester University is described. The machine architecture and underlying notation in which programs are expressed allow the exploitation of a parallelism in program execution at the instruction level. The processing subsystem may thus be designed as a parallel array of processing elements with a modular input/output interface. Faster execution rates can be achieved by the addition of more processing elements, so that a conventional bit-slice architecture is sufficient for their construction. The implementation of the machine order code is considered, and the instruction times are used to assess the subsystem performance. This should achieve an execution rate of 3. 3 MIPS with an array of 15 processing elements.
|Number of pages||7|
|Journal||IEE Proceedings E: Computers and Digital Techniques|
|Publication status||Published - Sept 1981|