TY - GEN
T1 - Design of resonant clock distribution networks for 3-D integrated circuits
AU - Rahimian, Somayyeh
AU - Pavlidis, Vasilis F.
AU - De Micheli, Giovanni
PY - 2011
Y1 - 2011
N2 - Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing clock signal to the sink nodes. A design method for 3-D resonant clock networks is presented. The proposed design technique supports resonant operation for pre-bond test, an important requirement for 3-D ICs. Several 3-D clock network topologies are explored in a 0.18 μm CMOS technology. Simulation results indicate 43% reduction in the power consumed by the resonant 3-D clock network as compared to a conventional buffered clock network.
AB - Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing clock signal to the sink nodes. A design method for 3-D resonant clock networks is presented. The proposed design technique supports resonant operation for pre-bond test, an important requirement for 3-D ICs. Several 3-D clock network topologies are explored in a 0.18 μm CMOS technology. Simulation results indicate 43% reduction in the power consumed by the resonant 3-D clock network as compared to a conventional buffered clock network.
KW - 3-D integration
KW - clock distribution networks
KW - resonant clocking
UR - http://www.scopus.com/inward/record.url?scp=80053524751&partnerID=8YFLogxK
U2 - 10.1007/978-3-642-24154-3_27
DO - 10.1007/978-3-642-24154-3_27
M3 - Conference contribution
AN - SCOPUS:80053524751
SN - 9783642241536
VL - 6951 LNCS
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 267
EP - 277
BT - Integrated Circuit and System Design: Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Proceedings
T2 - 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011
Y2 - 26 September 2011 through 29 September 2011
ER -