Designing Low-power, Low-latency Networks-on-chip by Optimally Combining Electrical and Optical Links

Sebastian Werner, Javier Navaridas, Mikel Luján

    Research output: Chapter in Book/Conference proceedingConference contributionpeer-review

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    Abstract

    Optical on-chip communication is considered a promising candidate to overcome latency and energy bottle-necks of electrical interconnects. Although recently proposed hybrid Networks-on-chip (NoCs), which implement both electrical and optical links, improve power eciency, they often fail to combine these two interconnect technologies eciently and suer from considerable
    laser power overheads caused by high-bandwidth optical links. We argue that these overheads can be avoided by inserting a higher quantity of low-bandwidth optical links in a topology, as this yields lower optical loss and
    in turn laser power. Moreover, when optimally combined with electrical links for short distances, this can be done without trading o latency. We present the effectiveness of this concept with Lego, our hybrid, mesh-based NoC that provides high power eciency by utilizing electrical links for local trac, and
    low-bandwidth optical links for long distances. Electrical links are placed systematically to outweigh the serialization delay introduced by the optical links, simplify router microarchitecture, and allow to save optical re-
    sources. Our routing algorithm always chooses the link that oers the lowest latency and energy. Compared to state-of-the-art proposals, Lego increases throughput-per-watt by at least 40%, and lowers latency by 35% on
    average for synthetic trac. On SPLASH-2/PARSEC workloads, Lego improves power eciency by at least 37% (up to 3.5).
    Original languageEnglish
    Title of host publicationThe 23rd IEEE Symposium on High Performance Computer Architecture
    PublisherIEEE
    DOIs
    Publication statusPublished - 4 Feb 2017
    EventThe 23rd IEEE Symposium on High Performance Computer Architecture - Austin, United States
    Duration: 4 Feb 20178 Feb 2017
    https://hpca2017.org/

    Publication series

    Name2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)
    PublisherIEEE
    ISSN (Electronic)2378-203X

    Conference

    ConferenceThe 23rd IEEE Symposium on High Performance Computer Architecture
    Abbreviated titleHPCA 2017
    Country/TerritoryUnited States
    CityAustin
    Period4/02/178/02/17
    Internet address

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