DiAD – Distributed Acceleration for Datacenter FPGAs

Joshua Lant, Emmanouil Skordalakis, Kyriakos Paraskevas, William B. Toms, Mikel Luján, John Goodacre

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

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Abstract

The growing demands placed upon modern compute and network resources are far exceeding the capabilities of traditional computer architectures. It is now customary for accelerators to perform the bulk of compute, and this compute is being pushed ever closer to the network. FPGA vendors have brought powerful datacenter cards to the market, combining reprogrammable FPGA fabrics with high bandwidth networking capability. However, the supporting infrastructure has yet to reach maturity, so modern and diverse workloads are not yet able to fully leverage these architectural advances.
In this paper we present DiAD; a novel framework providing FPGA firmware and driver support for fully unified, distributed compute and network acceleration across a commodity Ethernet network. We present a far richer feature set and greater flexibility than other existing solutions. We show comparable networking performance from the host when compared to Xilinx’s OpenNIC solution. As well as allowing for host networking through the FPGA fabric, we demonstrate reliable data transfer directly between FPGA fabrics without host intervention, and show native memory transactions sent over the network supporting pointer-chasing workloads. We achieve line rate for dataflow type communication and approach line rate for larger native memory transfers (87G).
Original languageEnglish
Title of host publicationProceedings of the 33rd International Conference on Field-Programmable Logic and Applications - FPL 2023
Number of pages8
DOIs
Publication statusE-pub ahead of print - 2 Nov 2023

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