Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware

Thomas Sharp; Cameron Patterson; Steve Furber

doi:10.1109/IJCNN.2011.6033346

Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware

Thomas Sharp, Cameron Patterson, Steve Furber

Advanced Processor Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

SpiNNaker is a massively-parallel neuromorphic computing architecture designed to model very large, biologically plausible spiking neural networks in real-time. A SpiNNaker machine consists of up to 216 homogeneous eighteen-core multiprocessor chips, each with an on-board router which forms links with neighbouring chips for packet-switched interprocessor communications. The architecture is designed for dynamic reconfiguration and optimised for transmission of neural activity data, which presents a challenge for machine configuration, program loading and simulation monitoring given a lack of globally-shared memory resources, intrinsic addressing mode or sideband configuration channel. We propose distributed software mechanisms to address these problems and present experiments which demonstrate the necessity of this approach in contrast to centralised mechanisms. © 2011 IEEE.

Original language	English
Title of host publication	Proceedings of the International Joint Conference on Neural Networks\|Proc Int Jt Conf Neural Networks
Place of Publication	USA
Publisher	IEEE
Pages	1099-1105
Number of pages	6
ISBN (Print)	9781457710865
DOIs	https://doi.org/10.1109/IJCNN.2011.6033346
Publication status	Published - 2011
Event	2011 International Joint Conference on Neural Network, IJCNN 2011 - San Jose, CA Duration: 1 Jul 2011 → … http://dx.doi.org/10.1109/IJCNN.2011.6033393

Conference

Conference	2011 International Joint Conference on Neural Network, IJCNN 2011
City	San Jose, CA
Period	1/07/11 → …
Internet address	http://dx.doi.org/10.1109/IJCNN.2011.6033393

Keywords

Computational modeling , Data models ,
Hardware , Monitoring , Read only memory ,
Routing , System software

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10.1109/IJCNN.2011.6033346

Cite this

@inproceedings{7d2bb175a8124c03b208ffd633d65a63,

title = "Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware",

abstract = "SpiNNaker is a massively-parallel neuromorphic computing architecture designed to model very large, biologically plausible spiking neural networks in real-time. A SpiNNaker machine consists of up to 216 homogeneous eighteen-core multiprocessor chips, each with an on-board router which forms links with neighbouring chips for packet-switched interprocessor communications. The architecture is designed for dynamic reconfiguration and optimised for transmission of neural activity data, which presents a challenge for machine configuration, program loading and simulation monitoring given a lack of globally-shared memory resources, intrinsic addressing mode or sideband configuration channel. We propose distributed software mechanisms to address these problems and present experiments which demonstrate the necessity of this approach in contrast to centralised mechanisms. {\textcopyright} 2011 IEEE.",

keywords = "Computational modeling , Data models ,, Hardware , Monitoring , Read only memory ,, Routing , System software",

author = "Thomas Sharp and Cameron Patterson and Steve Furber",

year = "2011",

doi = "10.1109/IJCNN.2011.6033346",

language = "English",

isbn = "9781457710865",

pages = "1099--1105",

booktitle = "Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks",

publisher = "IEEE",

address = "United States",

note = "2011 International Joint Conference on Neural Network, IJCNN 2011 ; Conference date: 01-07-2011",

url = "http://dx.doi.org/10.1109/IJCNN.2011.6033393",

}

Sharp, T, Patterson, C & Furber, S 2011, Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware. in Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks. IEEE, USA, pp. 1099-1105, 2011 International Joint Conference on Neural Network, IJCNN 2011, San Jose, CA, 1/07/11. https://doi.org/10.1109/IJCNN.2011.6033346

Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware. / Sharp, Thomas; Patterson, Cameron; Furber, Steve.
Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks. USA: IEEE, 2011. p. 1099-1105.

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware

AU - Sharp, Thomas

AU - Patterson, Cameron

AU - Furber, Steve

PY - 2011

Y1 - 2011

N2 - SpiNNaker is a massively-parallel neuromorphic computing architecture designed to model very large, biologically plausible spiking neural networks in real-time. A SpiNNaker machine consists of up to 216 homogeneous eighteen-core multiprocessor chips, each with an on-board router which forms links with neighbouring chips for packet-switched interprocessor communications. The architecture is designed for dynamic reconfiguration and optimised for transmission of neural activity data, which presents a challenge for machine configuration, program loading and simulation monitoring given a lack of globally-shared memory resources, intrinsic addressing mode or sideband configuration channel. We propose distributed software mechanisms to address these problems and present experiments which demonstrate the necessity of this approach in contrast to centralised mechanisms. © 2011 IEEE.

AB - SpiNNaker is a massively-parallel neuromorphic computing architecture designed to model very large, biologically plausible spiking neural networks in real-time. A SpiNNaker machine consists of up to 216 homogeneous eighteen-core multiprocessor chips, each with an on-board router which forms links with neighbouring chips for packet-switched interprocessor communications. The architecture is designed for dynamic reconfiguration and optimised for transmission of neural activity data, which presents a challenge for machine configuration, program loading and simulation monitoring given a lack of globally-shared memory resources, intrinsic addressing mode or sideband configuration channel. We propose distributed software mechanisms to address these problems and present experiments which demonstrate the necessity of this approach in contrast to centralised mechanisms. © 2011 IEEE.

KW - Computational modeling , Data models ,

KW - Hardware , Monitoring , Read only memory ,

KW - Routing , System software

U2 - 10.1109/IJCNN.2011.6033346

DO - 10.1109/IJCNN.2011.6033346

M3 - Conference contribution

SN - 9781457710865

SP - 1099

EP - 1105

BT - Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks

PB - IEEE

CY - USA

T2 - 2011 International Joint Conference on Neural Network, IJCNN 2011

Y2 - 1 July 2011

ER -

Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware

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Keywords

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