EFCAD – an Embedded FPGA CAD Tool Flow For Enabling On-Chip Self-Compilation

Khoa Pham; Malte Vesper; Dirk Koch; Eddie Hung

doi:10.1109/FCCM.2019.00011

EFCAD – an Embedded FPGA CAD Tool Flow For Enabling On-Chip Self-Compilation

Khoa Pham, Malte Vesper, Dirk Koch, Eddie Hung

Advanced Processor Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

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Abstract

This paper combines a chain of academic tools to form an FPGA compilation flow for building partially reconfigurable modules on lightweight embedded platforms. Our flow — EFCAD — supports the entire stack from RTL (Verilog) to (partial) bitstream, and we demonstrate early results from the onchip ARM processor of, and targeting, the latest 16nm generation of a Xilinx UltraScale+ FPGA-SoC device. With this, we complement Xilinx’s PYNQ initiative to not only facilitate System-on- Chip research and education entirely within an embedded system, but also to allow building new and specialising existing customcomputing accelerators without needing access to a workstation.

Original language	English
Title of host publication	The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines
DOIs	https://doi.org/10.1109/FCCM.2019.00011
Publication status	Published - 13 Jun 2019
Event	The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines - San Diego, United States Duration: 28 Apr 2019 → 1 May 2019

Conference

Conference	The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines
Abbreviated title	FCCM 2019
Country/Territory	United States
City	San Diego
Period	28/04/19 → 1/05/19

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10.1109/FCCM.2019.00011

FCCM2019_paper_195 (2)Accepted author manuscript, 349 KB

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@inproceedings{af10a4d7bf314ae7947e622b669d7027,

title = "EFCAD – an Embedded FPGA CAD Tool Flow For Enabling On-Chip Self-Compilation",

abstract = "This paper combines a chain of academic tools to form an FPGA compilation flow for building partially reconfigurable modules on lightweight embedded platforms. Our flow — EFCAD — supports the entire stack from RTL (Verilog) to (partial) bitstream, and we demonstrate early results from the onchip ARM processor of, and targeting, the latest 16nm generation of a Xilinx UltraScale+ FPGA-SoC device. With this, we complement Xilinx{\textquoteright}s PYNQ initiative to not only facilitate System-on- Chip research and education entirely within an embedded system, but also to allow building new and specialising existing customcomputing accelerators without needing access to a workstation.",

author = "Khoa Pham and Malte Vesper and Dirk Koch and Eddie Hung",

year = "2019",

month = jun,

day = "13",

doi = "10.1109/FCCM.2019.00011",

language = "English",

booktitle = "The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines",

note = "The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines, FCCM 2019 ; Conference date: 28-04-2019 Through 01-05-2019",

}

Pham, K, Vesper, M, Koch, D & Hung, E 2019, EFCAD – an Embedded FPGA CAD Tool Flow For Enabling On-Chip Self-Compilation. in The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines. The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines, San Diego, California, United States, 28/04/19. https://doi.org/10.1109/FCCM.2019.00011

TY - GEN

T1 - EFCAD – an Embedded FPGA CAD Tool Flow For Enabling On-Chip Self-Compilation

AU - Pham, Khoa

AU - Vesper, Malte

AU - Koch, Dirk

AU - Hung, Eddie

PY - 2019/6/13

Y1 - 2019/6/13

N2 - This paper combines a chain of academic tools to form an FPGA compilation flow for building partially reconfigurable modules on lightweight embedded platforms. Our flow — EFCAD — supports the entire stack from RTL (Verilog) to (partial) bitstream, and we demonstrate early results from the onchip ARM processor of, and targeting, the latest 16nm generation of a Xilinx UltraScale+ FPGA-SoC device. With this, we complement Xilinx’s PYNQ initiative to not only facilitate System-on- Chip research and education entirely within an embedded system, but also to allow building new and specialising existing customcomputing accelerators without needing access to a workstation.

AB - This paper combines a chain of academic tools to form an FPGA compilation flow for building partially reconfigurable modules on lightweight embedded platforms. Our flow — EFCAD — supports the entire stack from RTL (Verilog) to (partial) bitstream, and we demonstrate early results from the onchip ARM processor of, and targeting, the latest 16nm generation of a Xilinx UltraScale+ FPGA-SoC device. With this, we complement Xilinx’s PYNQ initiative to not only facilitate System-on- Chip research and education entirely within an embedded system, but also to allow building new and specialising existing customcomputing accelerators without needing access to a workstation.

U2 - 10.1109/FCCM.2019.00011

DO - 10.1109/FCCM.2019.00011

M3 - Conference contribution

BT - The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines

T2 - The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines

Y2 - 28 April 2019 through 1 May 2019

ER -

EFCAD – an Embedded FPGA CAD Tool Flow For Enabling On-Chip Self-Compilation

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