Enabling Dynamic System Integration on Maxeler HLS Platforms

Charalampos Kritikakis, Dirk Koch

Research output: Contribution to journalArticlepeer-review


High Level Synthesis (HLS) tools enable application domain experts to implement applications and algorithms on FPGAs. The majority of present FPGA applications is following a stream processing model which is almost entirely implemented statically and not exploiting the benefits enabled by partial reconfiguration. In this paper, we propose a generic approach for implementing and using partial reconfiguration through an HLS design flow for Maxeler platforms. Our flow extracts HLS generated HDL code from the Maxeler compilation process in order to implement a static FPGA infrastructure as well as run-time reconfigurable stream processing modules. As a distinct feature, our infrastructure can accommodate multiple partial modules in a pipeline daisy-chained manner, which aligns directly to Maxeler’s dataflow programming paradigm. The benefits of the proposed flow are demonstrated by a case study of a dynamically reconfigurable video processing pipeline delivering 6.4GB/s throughput.

Original languageEnglish
Pages (from-to)887-905
JournalJournal of Signal Processing Systems
Issue number9
Early online date9 Aug 2020
Publication statusPublished - 1 Sept 2020


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