Energy-Efficient Encoding for High-Speed Serial Interfaces

Energy consumption has become a bottleneck in modern ICs with a significant part of the energy spent on data communication. High-speed, serial interfaces are widely used, offering important advantages over parallel buses. The energy demand of source synchronous, serial buses can be effectively decreased by employing encoding techniques that reduce the bit transitions of the transmitted data stream. However, these techniques are not applicable for asynchronous interfaces, such as PCIe, where frequent bit transitions are required to recover the clock at the receiver to maintain link integrity. Recognising this fundamental trait, an encoding technique named STTE is proposed that regulates the number of transitions such that the clock can be reliably recovered while the communication energy is lowered. The proposed scheme provides at least 25% decrease in energy for a short interposer-based interconnect compared to scrambling, which is typically used in SerDes devices. The link integrity is experimentally evaluated using both an electrical and an optical link that interconnect two FPGA devices. Results demonstrate that STTE successfully preserves link integrity as no errors are induced during transmission. In addition, STTE adjusts the number of transitions, thus, allowing energy reduction and link integrity to be traded-off.