TY - JOUR
T1 - Energy-Efficient Time-Based Adaptive Encoding for Off-Chip Communication
AU - Maragkoudaki, Eleni
AU - Pavlidis, Vasilis
N1 - Funding Information:
Manuscript received January 10, 2020; revised June 1, 2020 and July 23, 2020; accepted August 8, 2020. Date of publication August 31, 2020; date of current version November 24, 2020. This work was supported in part by the European Commission through the Horizon 2020 Framework Programme for Research and Innovation within the EuroExa Project under Grant 754337. (Corresponding author: Eleni Maragkoudaki.) The authors are with the Advanced Processor Technology Group, School of Computer Science, The University of Manchester, Manchester M13 9PL, U.K. (e-mail: eleni.maragkoudaki@manchester.ac.uk; pavlidis@cs.man.ac.uk).
Publisher Copyright:
© 1993-2012 IEEE.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2020/8/31
Y1 - 2020/8/31
N2 - The energy for data transfer has an increasing effect on the total system energy as technology scales, often overtaking computation energy. To reduce the power of interchip interconnects, an adaptive encoding scheme called Adaptive Word Reordering (AWR) is proposed that effectively decreases the number of signal transitions, leading to a significant power reduction. A novel circuit is implemented which exploits the time domain to represent complex bit transition computations as delays and, thus, limits the power overhead due to encoding.The effectiveness of AWR is validated in terms of decrease in both bit transitions and power consumption. AWR is shown to yield higher power savings compared to three state-of-the-art techniques reaching 23% and 61% during the transfer of multiplexed address-data and image files, respectively, at just 1 mm wire length.
AB - The energy for data transfer has an increasing effect on the total system energy as technology scales, often overtaking computation energy. To reduce the power of interchip interconnects, an adaptive encoding scheme called Adaptive Word Reordering (AWR) is proposed that effectively decreases the number of signal transitions, leading to a significant power reduction. A novel circuit is implemented which exploits the time domain to represent complex bit transition computations as delays and, thus, limits the power overhead due to encoding.The effectiveness of AWR is validated in terms of decrease in both bit transitions and power consumption. AWR is shown to yield higher power savings compared to three state-of-the-art techniques reaching 23% and 61% during the transfer of multiplexed address-data and image files, respectively, at just 1 mm wire length.
U2 - 10.1109/TVLSI.2020.3018062
DO - 10.1109/TVLSI.2020.3018062
M3 - Article
VL - 28
SP - 2551
EP - 2562
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 12
M1 - 9180343
ER -