Event-driven configuration of a neural network CMP system over a homogeneous interconnect fabric

M. M. Khan, J. Navaridas, A. D. Rast, X. Jin, Luis A. Plana, M. Luján, J. V. Woods, J. Miguel-Alonso, S. B. Furber

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Configuring a million-core parallel system at boot time is a difficult process when the system has neither specialised hardware support for the configuration process nor a preconfigured default state that puts it in operating condition. SpiNNaker is a parallel Chip Multiprocessor (CMP) system for neural network (NN) simulation. Where most large CMP systems feature a sideband network to complete the boot process, SpiNNaker has a single homogeneous network interconnect for both application inter-processor communications and system control functions such as boot load and run-time user-system interaction. This network improves fault tolerance and makes it easier to support dynamic run-time reconfiguration, however, it requires a boot process that is transaction-level compatible with the application's communications model. Since SpiNNaker uses event-driven asynchronous communications throughout, the loader operates with purely local control: there is no global synchronisation, state information, or transition sequence. A novel two-stage "unfolding" boot-up process efficiently configures the SpiNNaker hardware and loads the application using a high-speed flood-fill technique with support for run-time reconfiguration. SystemC simulation of a multi-CMP SpiNNaker system indicates an error-free CMP configuration time of 1.3 ms, while a high-level simulation of a full-scale system (64K CMPs) indicates a mean application-loading time of ∼20ms (for a 100KB application), which is virtually independent of the size of the system. We verified the CMP configuration process with hardware-level Verilog simulation. © 2009 IEEE.
Original languageEnglish
Title of host publication8th International Symposium on Parallel and Distributed Computing, ISPDC 2009|Int. Symp. Parallel Distrib. Comput., ISPDC
Place of PublicationUSA
PublisherIEEE
Pages54-61
Number of pages7
ISBN (Print)9780769536804
DOIs
Publication statusPublished - 2009
Event8th International Symposium on Parallel and Distributed Computing, ISPDC 2009 - Lisbon
Duration: 1 Jul 2009 → …

Conference

Conference8th International Symposium on Parallel and Distributed Computing, ISPDC 2009
CityLisbon
Period1/07/09 → …

Keywords

  • multiprocessor interconnection networks
  • fault tolerant computing
  • asynchronous circuits
  • neural nets
  • parallel processing

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