Exploiting Synchrony for Area and Performance Improvement in the Asynchronous Domain

Mahdi Jelodari Mamaghani, Jim Garside

Research output: Chapter in Book/Conference proceedingConference contributionpeer-review

57 Downloads (Pure)

Abstract

This work proposes a synthesis process called ‘eTeak’ which exploits synchronous EDAs to improve the implemented circuits. In this regard, it incorporates the synchronous elastic protocol in the Teak synthesis flow to move fine-grained concurrency from the asynchronous into the synchronous domain where clocked CAD tools can optimise the data manipulation units. A transformation technique is also proposed to enable the designer to explore the level of elasticity in the network and trade off the costs associated with computation and communication.
Original languageEnglish
Title of host publicationBook of Abstracts
Place of PublicationGermany
PublisherIEEE Computer Society
Pages46-48
Number of pages3
Publication statusPublished - May 2014
EventInternational Symposium on Asynchronous Circuits and Systems (ASYNC) - Potsdam, Germany
Duration: 11 May 201414 May 2014

Conference

ConferenceInternational Symposium on Asynchronous Circuits and Systems (ASYNC)
CityPotsdam, Germany
Period11/05/1414/05/14

Keywords

  • Asynchronous CAD
  • Synchronous Elastic Systems
  • Asynchronous Dataflows
  • Distributed Control Architecture

Fingerprint

Dive into the research topics of 'Exploiting Synchrony for Area and Performance Improvement in the Asynchronous Domain'. Together they form a unique fingerprint.

Cite this