Exploring embedded symmetric multiprocessing with various on-chip architectures

Multicore embedded systems have evolved to appear in different domains. In this paper, we explore and compare various on-chip architectures with respect to a number design metrics. Unlike earlier published works that majorly concern with optimizations in processor, memory and cache hierarchies, in this paper, we aim to ascertain the best on-chip architectures for given processor cores, Level 1-2-3 caches modeled from Intel Atom embedded processor family. We investigate topologies that haven't been considered before for symmetric multiprocessing in embedded systems domain. These architectures consist of shared instruction caches between cores and heterogenous cache topologies that feature bypassing a level in the cache hierarchy. Through our experiments with multithreaded workloads, we elicit the unconventional topologies that could provide more performance and energy efficiency than regular topologies. In addition, using our experimental data, we conclude that certain design metrics could depend on given workload, however there also exists some metrics that are more dependent on the the underlying topologies. Thus, we urge the need for future exploration tools to gather the necessary metrics while choosing the appropriate SMP architectures.