Abstract
Asynchronous hand-shaken inter-chip links are very popular among neuromorphic full-custom chips due to their delay insensitive and high-speed properties. Of special interest are those links that minimize bit-line transitions for power saving, like the 2-phase hand-shaken NRZ (Non Return to Zero) 2-of-7 protocol used in the commercial SpiNNaker chips. Interfacing such custom chip links to FPGAs is always of great interest, so that additional functionalities can be experimented and exploited for producing more versatile systems. Present day commercial FPGAs operate typically in synchronous mode, thus making it necessary to incorporate synchronizers when interfacing with asynchronous chips. This introduces extra latencies and precludes pipelining, deteriorating transmission speed, especially when sending multi-symbols per unit communication packet. In this paper we present a technique that learns to estimate the delay of a symbol transaction, thus allowing a fast pipelining from symbol to symbol. The technique has been tested on links between FPGAs and SpiNNaker chips, achieving the same throughput as fully asynchronous synchronizer-less links between SpiNNaker chips. The links have been tested for periods of over one week without any transaction failure. Verilog codes of FPGA circuits will be available as additional material for download.
Original language | English |
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Pages (from-to) | 763-767 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems. Part 2: Express Briefs |
Volume | 63 |
Issue number | 8 |
DOIs | |
Publication status | Published - 18 Feb 2016 |
Keywords
- Clocks;Delays;Field programmable gate arrays;Optical signal processing;Receivers;Registers;Synchronization;Address event representation (AER);asynchronous links;event-driven links;field-programmable gate arrays (FPGAs);neuromorphic chips;synchronization