Abstract
Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologies using this system have always yielded very slow designs. Early output logic is a method which aims to improve the performance of QDI circuits without decreasing their robustness. In order to force QDI restrictions on early output circuits a form of guarding is necessary. This paper presents a new form of guarding which allows partial stage completion allowing desynchronisation of inputs. This is shown to be highly advantageous in cases where the previous style performed poorly. Because the two styles can be mixed, the designs no longer suffer from very poor performance of some QDI constructions. © 2009 IEEE.
Original language | English |
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Title of host publication | Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009|Proc. IEEE Symp. Des. Diagn. Electron. Circuits Syst., DDECS |
Publisher | IEEE Computer Society |
Pages | 226-229 |
Number of pages | 3 |
ISBN (Print) | 9781424433391 |
DOIs | |
Publication status | Published - 2009 |
Event | 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009 - Liberec Duration: 1 Jul 2009 → … http://dblp.uni-trier.de/db/conf/ddecs/ddecs2009.html#BrejE09http://dblp.uni-trier.de/rec/bibtex/conf/ddecs/BrejE09.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/ddecs/BrejE09 |
Conference
Conference | 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009 |
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City | Liberec |
Period | 1/07/09 → … |
Internet address |