@article{603bcddc6e1f45f7b7b00caca4ea8a9a,
title = "FOS: A Modular FPGA Operating System for Dynamic Workloads",
abstract = "With FPGAs now being deployed in the cloud and at the edge, there is a need for scalable design methods that can incorporate the heterogeneity present in the hardware and software components of FPGA systems. Moreover, these FPGA systems need to be maintainable and adaptable to changing workloads while improving accessibility for the application developers. However, current FPGA systems fail to achieve modularity and support for multi-tenancy due to dependencies between system components and lack of standardized abstraction layers. To solve this, we introduce a modular FPGA operating system -- FOS, which adopts a modular FPGA development flow to allow each system component to be changed and be agnostic to the heterogeneity of EDA tool versions, hardware and software layers. Further, to dynamically maximize the utilization transparently from the users, FOS employs resource-elastic scheduling to arbitrate the FPGA resources in both time and spatial domain for any type of accelerators. Our evaluation on different FPGA boards shows that FOS can provide performance improvements in both single-tenant and multi-tenant environments while substantially reducing the development time and, at the same time, improving flexibility.",
keywords = "FPGA, FPGA shell, dynamic workloads, high-level synthesis, modular development, operating system, resource-elasticity, runtime systems",
author = "Anuj Vaishnav and Khoa Pham and Joseph Powell and Dirk Koch",
note = "Funding Information: This work is supported by (1) the European Commission under the H2020 Program and the EuroEXA project (grant agreement 754337) and (2) the UK Research Institute in Secure Hardware and Embedded Systems (RISE) through the project rFAS -reconfigurable FPGA Accelerator Sandboxing (grant agreement 4212204/RFA 15971). We also thank the Xilinx University Program for providing tools and boards. Authors{\textquoteright} addresses: A. Vaishnav, K. D. Pham, J. Powell, and D. Koch, Advanced Processor Technologies Research Group, Information Technology Building, Department of Computer Science, The University of Manchester, Oxford Rd, Manchester M13 9PL, UK; emails: {anuj.vaishnav, khoa.pham, joseph.powell, dirk.koch}@manchester.ac.uk. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. {\textcopyright} 2020 Copyright held by the owner/author(s). Publication rights licensed to ACM. 1936-7406/2020/09-ART20 $15.00 https://doi.org/10.1145/3405794 Publisher Copyright: {\textcopyright} 2020 ACM. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.",
year = "2020",
month = oct,
doi = "https://doi.org/10.1145/3405794",
language = "English",
volume = "13",
journal = "ACM Transactions on Reconfigurable Technology and Systems",
issn = "1936-7406",
publisher = "ACM Special Interest Group",
number = "4",
}