FPGA based gate signal generator for three-level neutral point clamped inverters

M.R. Ahmed, D.J. Rogers

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Abstract

The gate signals in a commercial three-phase two-level induction motor drive are translated to operate a three-phase three-level neutral point clamped (NPC) inverter. An FPGA is used to demodulate the two-level gate signals and then to generate NPC gate drive signals by re-modulation. A sine PWM modulation strategy with in-phase disposition of carriers is used to generate NPC gate drive signals. The modulation strategy is simulated first and then implemented using an Altera FPGA. The close match between the simulation and experimental results proves the concept and demonstrates the accuracy of this unique modulation technique.
Original languageEnglish
Title of host publicationhost publication
PublisherIEEE
Publication statusPublished - Jun 2015
Event9th International Conference on Compatibility and Power Electronics (CPE), 2015 - Lisbon, Portugal
Duration: 24 Jun 201526 Jun 2015

Conference

Conference9th International Conference on Compatibility and Power Electronics (CPE), 2015
CityLisbon, Portugal
Period24/06/1526/06/15

Keywords

  • FPGA , three-level neutral point clamped inverter, modulation strategy of NPC inverter, VHDL code, sine PWM

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