FPGA implementation of a simple approach for jitter minimisation in Ethernet for real-time control communication

An approach for cheap and deterministic control communication using Ethernet real-time control communication is presented. Field-programmable gate array (FPGA) technology, i.e Xilinx XC3S500E from the Spartan-3E family, is used to implement the Ethernet communication strategy. The unit is defined in Verilog using Xilinx ISE 11.1 software tools. Data packages are sent at well defined times to avoid collisions. Collisions mainly occur due to jitter of the transmitter system, so that arbitration (similar to CANopen) is necessary. The Binary Exponential Backoff (BEB) scheme is used. This paper analyzes and investigates how the backoff time affects the performance of the Carrier Sense Multiple Access protocol with Collision Detection (CSMA/CD) in a basic Media Access Controller (MAC), in terms of data arrival characteristics, i.e jitter and delay. We propose to assign different minimal backoff times for each of the CSMA/CD controller units to minimize packet collisions. The proposed hardware design shows the advantage of our approach over a standard CSMA/CD setting.