GaN metal-oxide-semiconductor high-electron-mobility transistors using thermally evaporated SiO as the gate dielectric

GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with thermally evaporated SiO gate dielectric of different thicknesses (10–30 nm) have been investigated and compared with standard metal–semiconductor HEMT (MES-HEMT). Unlike typical dielectrics for GaN MOS-HEMTs that require deposition with ion bombardments, reactive gases and/or high temperatures, thermally evaporated SiO is expected to introduce little damage to the interface. Indeed, a lower sheet resistance and higher drain current were obtained in the SiO-based MOS-HEMTs than in the MES-HEMT. In addition, significantly lower off-state drain currents and higher I on/I off ratios were obtained in the MOS-HEMTs. Importantly, the interface trap density in the MOS-HEMTs, ~1.0 × 1012 cm−2 eV−1, was found to be significantly lower than that in MES-HEMT (2.4 × 1012 cm−2 eV−1). This enables the SiO MOS-HEMTs to exhibit drastic improvements not only in the leakage currents and breakdown voltage, but also in the drain current collapse and high frequency performance. The optimized 30 nm SiO MOS-HEMT has a 438 times higher I on/I off ratio (1.4 × 108), two orders of magnitude lower off-state drain current and gate leakage current, and 100 V higher breakdown voltage as compared to the MES-HEMT. Our study may have important implications in realizing high performance, low damage and low cost gate dielectrics for GaN HEMTs.