Gate recess study for high thermal stability pHEMT devices

M. Mohamad Isa; N. Ahmad; Siti S. Mat Isa; Muhammad M. Ramli; N. Khalid; N. I.M. Nor; S. R. Kasjoo; M. Missous

doi:10.1051/epjconf/201716201047

Gate recess study for high thermal stability pHEMT devices

M. Mohamad Isa^*, N. Ahmad, Siti S. Mat Isa, Muhammad M. Ramli, N. Khalid, N. I.M. Nor, S. R. Kasjoo, M. Missous

^*Corresponding author for this work

Universiti Malaysai Perlis

Research output: Contribution to journal › Conference article › peer-review

Abstract

Gate formation is a crucial steps, especially in FET fabrication process. At this steps, the characteristics are very much influenced by the processing parameters, particularly in the processing temperature. In this paper, we report the thermal stability study and sidewall etch to reduce the off-state Schottky's gate leakage on 1 μm gate pHEMT device. In our study, we found that low sintering temperatures of 200°C is preferable and sidewall etching of 10 minutes has reduces the gate leakage by almost 5 times as compared with the devices with no sidewall etching. The optimised processing recipe is proposed for low off-state Schottky's gate leakage, where low leakage has significant influence in the device performances, especially for future high speed and low noise applications.

Original language	English
Article number	01047
Journal	EPJ Web of Conferences
Volume	162
DOIs	https://doi.org/10.1051/epjconf/201716201047
Publication status	Published - 22 Nov 2017
Event	2017 International Conference on Applied Photonics and Electronics, InCAPE 2017 - Port Dickson, N. Sembilan, Malaysia Duration: 9 Aug 2017 → 10 Aug 2017

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title = "Gate recess study for high thermal stability pHEMT devices",

abstract = "Gate formation is a crucial steps, especially in FET fabrication process. At this steps, the characteristics are very much influenced by the processing parameters, particularly in the processing temperature. In this paper, we report the thermal stability study and sidewall etch to reduce the off-state Schottky's gate leakage on 1 μm gate pHEMT device. In our study, we found that low sintering temperatures of 200°C is preferable and sidewall etching of 10 minutes has reduces the gate leakage by almost 5 times as compared with the devices with no sidewall etching. The optimised processing recipe is proposed for low off-state Schottky's gate leakage, where low leakage has significant influence in the device performances, especially for future high speed and low noise applications.",

author = "Isa, {M. Mohamad} and N. Ahmad and {Mat Isa}, {Siti S.} and Ramli, {Muhammad M.} and N. Khalid and Nor, {N. I.M.} and Kasjoo, {S. R.} and M. Missous",

year = "2017",

month = nov,

day = "22",

doi = "10.1051/epjconf/201716201047",

language = "English",

volume = "162",

journal = "EPJ Web of Conferences",

issn = "2101-6275",

publisher = "EDP Sciences",

note = "2017 International Conference on Applied Photonics and Electronics, InCAPE 2017 ; Conference date: 09-08-2017 Through 10-08-2017",

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TY - JOUR

T1 - Gate recess study for high thermal stability pHEMT devices

AU - Isa, M. Mohamad

AU - Ahmad, N.

AU - Mat Isa, Siti S.

AU - Ramli, Muhammad M.

AU - Khalid, N.

AU - Nor, N. I.M.

AU - Kasjoo, S. R.

AU - Missous, M.

PY - 2017/11/22

Y1 - 2017/11/22

N2 - Gate formation is a crucial steps, especially in FET fabrication process. At this steps, the characteristics are very much influenced by the processing parameters, particularly in the processing temperature. In this paper, we report the thermal stability study and sidewall etch to reduce the off-state Schottky's gate leakage on 1 μm gate pHEMT device. In our study, we found that low sintering temperatures of 200°C is preferable and sidewall etching of 10 minutes has reduces the gate leakage by almost 5 times as compared with the devices with no sidewall etching. The optimised processing recipe is proposed for low off-state Schottky's gate leakage, where low leakage has significant influence in the device performances, especially for future high speed and low noise applications.

AB - Gate formation is a crucial steps, especially in FET fabrication process. At this steps, the characteristics are very much influenced by the processing parameters, particularly in the processing temperature. In this paper, we report the thermal stability study and sidewall etch to reduce the off-state Schottky's gate leakage on 1 μm gate pHEMT device. In our study, we found that low sintering temperatures of 200°C is preferable and sidewall etching of 10 minutes has reduces the gate leakage by almost 5 times as compared with the devices with no sidewall etching. The optimised processing recipe is proposed for low off-state Schottky's gate leakage, where low leakage has significant influence in the device performances, especially for future high speed and low noise applications.

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U2 - 10.1051/epjconf/201716201047

DO - 10.1051/epjconf/201716201047

M3 - Conference article

AN - SCOPUS:85036656092

SN - 2101-6275

VL - 162

JO - EPJ Web of Conferences

JF - EPJ Web of Conferences

M1 - 01047

T2 - 2017 International Conference on Applied Photonics and Electronics, InCAPE 2017

Y2 - 9 August 2017 through 10 August 2017

ER -

Gate recess study for high thermal stability pHEMT devices

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