Gate recess study for high thermal stability pHEMT devices

M. Mohamad Isa, N. Ahmad, Siti S. Mat Isa, Muhammad M. Ramli, N. Khalid, N. I.M. Nor, S. R. Kasjoo, M. Missous

Research output: Contribution to journalConference articlepeer-review

Abstract

Gate formation is a crucial steps, especially in FET fabrication process. At this steps, the characteristics are very much influenced by the processing parameters, particularly in the processing temperature. In this paper, we report the thermal stability study and sidewall etch to reduce the off-state Schottky's gate leakage on 1 μm gate pHEMT device. In our study, we found that low sintering temperatures of 200°C is preferable and sidewall etching of 10 minutes has reduces the gate leakage by almost 5 times as compared with the devices with no sidewall etching. The optimised processing recipe is proposed for low off-state Schottky's gate leakage, where low leakage has significant influence in the device performances, especially for future high speed and low noise applications.

Original languageEnglish
Article number01047
JournalEPJ Web of Conferences
Volume162
DOIs
Publication statusPublished - 22 Nov 2017
Event2017 International Conference on Applied Photonics and Electronics, InCAPE 2017 - Port Dickson, N. Sembilan, Malaysia
Duration: 9 Aug 201710 Aug 2017

Fingerprint

Dive into the research topics of 'Gate recess study for high thermal stability pHEMT devices'. Together they form a unique fingerprint.

Cite this