Hardware Measurement of MMC Time Delay and its Impact on the Stability of Grid-connected MMC-HVDC Systems

Time delay in the feedback loop of power electronic converter control has the potential to induce poor response and even instability. In many published models of Modular Multilevel Converters High Voltage Direct Current (MMC-HVDC) systems this time delay has, however, been assumed negligible. In contrast, this paper finds that this parameter, which we refer to as the Total System Time
Delay (TSTD), can be significant within MMCs, based on tests shown for a laboratory-scale converter hardware prototype with an industrially representative distributed control architecture. Given MMC complex multi-layer control structures, this may affect the control speed, system stability and ancillary service provision. When used in previous publications, the time delay was typically based on rough estimation, this paper provides a breakdown and explanation of the TSTD, identifying a TSTD range of 135 - 235 µs for industrial-scale MMCs. This finding is then used to undertake an impact analysis for a 1 GW MMC-HVDC system. First, a small-signal state-space model of the MMC-HVDC system is established and the impact of the TSTD on stability is assessed based
on the generalized Nyquist stability criterion. The analysis is then verified through non-linear time-domain simulations in PSCAD/EMTDC. The results reveal that the identified industrial TSTD range requires a network short circuit ratio greater than
2.95 to ensure stability at rated power outputs.