Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures

Anuj Vaishnav, Khoa Pham, Dirk Koch

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


Heterogeneous computing is a key strategy to meet the requirements of many compute-intensive applications. However, currently, CPU+FPGA platforms are commonly underutilized as scheduling is often constrained to a run-to-completion model or acceleration of a single application at a time. To tackle this issue, this paper proposes heterogeneous resource-elastic scheduling for maximizing the utilization of both CPU and FPGA resources by dynamically scaling the resource allocation for tasks transparently. It achieves this for heterogeneous workloads (OpenCL) by selecting the number of compute units, accelerator type and device types using partial reconfiguration and cooperative fine-grained scheduling for maximizing system performance based on runtime conditions. We demonstrate as much as 2x better performance as compared to SDSoC-like platforms and on average 20% improvement in performance as compared to other standard scheduling algorithms while lowering task wait times. Our results indicate that 1) workload can be executed seamlessly on both CPU and FPGA without increasing programming effort and 2) co-scheduling applications on heterogeneous systems can improve system performance.
Original languageEnglish
Title of host publication 10th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)
PublisherACM Digital Library
ISBN (Electronic)978-1-4503-7255-8
Publication statusPublished - 6 Jun 2019


  • Heterogeneous computing
  • FPGAs
  • OpenCL
  • Runtime systems


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