Implementation of simd vision chip with 128x128 array of analogue processing elements

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    Abstract

    This paper presents the latest implementation of the SIMD Current-mode Analogue Matrix Processor architecture. The SCAMP-3 vision chip has been fabricated in a 0.35μm CMOS technology and comprises a 128×128 general-purpose programmable processor-perpixel array. The architecture of the chip is overviewed and implementation issues are considered. The circuit design of the analogue register is presented, the layout of the Analogue Processing Element is discussed and the design of control-signal drivers and readout circuitry is overviewed. © 2005 IEEE.
    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst
    Pages5806-5809
    Number of pages3
    DOIs
    Publication statusPublished - 2005
    EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe
    Duration: 1 Jul 2005 → …

    Conference

    ConferenceIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
    CityKobe
    Period1/07/05 → …

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