Improving performance by reducing aborts in hardware transactional memory

Mohammad Ansari, Behram Khan, Mikel Luján, Christos Kotselidis, Chris Kirkham, Ian Watson

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


    The optimistic nature of Transactional Memory (TM) systems can lead to the concurrent execution of transactions that are later found to conflict. Conflicts degrade scalability, and may lead to aborts that increase wasted work, and degrade performance. A promising approach to reducing conflicts at runtime is dynamically, and transparently, reordering the execution of transactions upon discovery of conflicts. This approach has been explored in Software TMs (STMs), but not in Hardware TMs (HTMs). Furthermore, STM implementations of this approach cannot be ported to HTMs easily. This paper investigates the feasibility of such reordering in HTMs, and presents two designs that are scalable, independent of the on-chip interconnect, require only minor modifications to each core, and add no execution overhead if no conflicts occur. The evaluation takes LogTM-SE as a base line and considers benchmarks with different levels of contention (transactional conflicts). The results show that the preferred design increases HTM performance by up to 17% when contention is low, 57% when contention is high, and never degrades performance. Finally, the designs are orthogonal to LogTM-SE; they require no modification to cache structures, and continue to support transaction virtualization, open and closed unbounded nesting, paging, thread suspension, and thread migration. © 2010 Springer-Verlag.
    Original languageEnglish
    Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|Lect. Notes Comput. Sci.
    Place of PublicationBerlin / Heidelberg
    PublisherSpringer Nature
    Number of pages14
    ISBN (Print)3642115144, 9783642115141
    Publication statusPublished - 2010
    Event5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010 - Pisa
    Duration: 1 Jul 2010 → …


    Conference5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010
    Period1/07/10 → …


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