A systematic investigation has been undertaken, in which thin polymer buffer layers with different ester content have been spin-coated onto a flash-evaporated, cross-linked diacrylate gate-insulator to form bottom-gate, top-contact organic thin-film transistors. The highest device mobilities, ∼0.65 cm2/V s and ∼1.00 cm2/V s for pentacene and dinaphtho[2,3-b:2′,3′-f]-thieno[3,2-b]thiophene (DNTT), respectively, were only observed for a combination of large-grain (∼1-2 μm) semiconductor morphology coupled with a non-polar dielectric surface. No correlation was found between semiconductor grain size and dielectric surface chemistry. The threshold voltage of pentacene devices shifted from -10 V to -25 V with decreasing surface ester content, but remained close to 0 V for DNTT. © 2013 AIP Publishing LLC.