Integrated circuit implementation of a compact discrete-time chaos generator

V. D. Juncu; M. Rafiei-Naeini; P. Dudek

doi:10.1007/s10470-006-1432-0

Integrated circuit implementation of a compact discrete-time chaos generator

V. D. Juncu, M. Rafiei-Naeini, P. Dudek

Research output: Contribution to journal › Article › peer-review

Abstract

A discrete-time chaos generator implemented with two nonlinear circuit cells has been fabricated in a 0.6 μm CMOS technology. Each cell is creating a function (map) which allows a chaos signal to be generated. Measurements of the chip were performed with a supply voltage of 5 V, up to a frequency of 2.5 MHz. A bifurcation diagram of the circuit and the Lyapunov exponent calculation are presented. The size of the generator layout (without the switches) is 32 × 19 μ m which makes it suitable for applications where many chaos signal generators are required on a single chip. © 2006 Springer Science + Business Media, Inc.

Original language	English
Pages (from-to)	275-280
Number of pages	5
Journal	Analog Integrated Circuits and Signal Processing
Volume	46
Issue number	3
DOIs	https://doi.org/10.1007/s10470-006-1432-0
Publication status	Published - Mar 2006

Keywords

Bifurcation diagram
Chaos generator
Lyapunov exponent
Map circuit
Random noise generator

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10.1007/s10470-006-1432-0

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title = "Integrated circuit implementation of a compact discrete-time chaos generator",

abstract = "A discrete-time chaos generator implemented with two nonlinear circuit cells has been fabricated in a 0.6 μm CMOS technology. Each cell is creating a function (map) which allows a chaos signal to be generated. Measurements of the chip were performed with a supply voltage of 5 V, up to a frequency of 2.5 MHz. A bifurcation diagram of the circuit and the Lyapunov exponent calculation are presented. The size of the generator layout (without the switches) is 32 × 19 μ m which makes it suitable for applications where many chaos signal generators are required on a single chip. {\textcopyright} 2006 Springer Science + Business Media, Inc.",

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AU - Rafiei-Naeini, M.

AU - Dudek, P.

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N2 - A discrete-time chaos generator implemented with two nonlinear circuit cells has been fabricated in a 0.6 μm CMOS technology. Each cell is creating a function (map) which allows a chaos signal to be generated. Measurements of the chip were performed with a supply voltage of 5 V, up to a frequency of 2.5 MHz. A bifurcation diagram of the circuit and the Lyapunov exponent calculation are presented. The size of the generator layout (without the switches) is 32 × 19 μ m which makes it suitable for applications where many chaos signal generators are required on a single chip. © 2006 Springer Science + Business Media, Inc.

AB - A discrete-time chaos generator implemented with two nonlinear circuit cells has been fabricated in a 0.6 μm CMOS technology. Each cell is creating a function (map) which allows a chaos signal to be generated. Measurements of the chip were performed with a supply voltage of 5 V, up to a frequency of 2.5 MHz. A bifurcation diagram of the circuit and the Lyapunov exponent calculation are presented. The size of the generator layout (without the switches) is 32 × 19 μ m which makes it suitable for applications where many chaos signal generators are required on a single chip. © 2006 Springer Science + Business Media, Inc.

KW - Bifurcation diagram

KW - Chaos generator

KW - Lyapunov exponent

KW - Map circuit

KW - Random noise generator

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JO - Analog Integrated Circuits and Signal Processing

JF - Analog Integrated Circuits and Signal Processing

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ER -

Integrated circuit implementation of a compact discrete-time chaos generator

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Keywords

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