Integrated circuit implementation of a cortical neuron

Jayawan H B Wijekoon; Piotr Dudek

doi:10.1109/ISCAS.2008.4541785

Integrated circuit implementation of a cortical neuron

Jayawan H B Wijekoon, Piotr Dudek

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 μm CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking and bursting firing patterns. The models of various cortical neuron types are obtained in a single circuit, through the adjustment of two biasing voltages, making the circuit suitable for applications in reconfigurable neuromorphic devices that implement biologically plausible spiking neural networks. ©2008 IEEE.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems\|Proc IEEE Int Symp Circuits Syst
Pages	1784-1787
Number of pages	3
DOIs	https://doi.org/10.1109/ISCAS.2008.4541785
Publication status	Published - 2008
Event	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA Duration: 1 Jul 2008 → …

Conference

Conference	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
City	Seattle, WA
Period	1/07/08 → …

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10.1109/ISCAS.2008.4541785

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@inproceedings{4c662ab4d56f4714866a51717697278a,

title = "Integrated circuit implementation of a cortical neuron",

abstract = "This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 μm CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking and bursting firing patterns. The models of various cortical neuron types are obtained in a single circuit, through the adjustment of two biasing voltages, making the circuit suitable for applications in reconfigurable neuromorphic devices that implement biologically plausible spiking neural networks. {\textcopyright}2008 IEEE.",

author = "Wijekoon, {Jayawan H B} and Piotr Dudek",

year = "2008",

doi = "10.1109/ISCAS.2008.4541785",

language = "English",

isbn = "9781424416844",

pages = "1784--1787",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst",

note = "2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 ; Conference date: 01-07-2008",

}

TY - GEN

T1 - Integrated circuit implementation of a cortical neuron

AU - Wijekoon, Jayawan H B

AU - Dudek, Piotr

PY - 2008

Y1 - 2008

N2 - This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 μm CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking and bursting firing patterns. The models of various cortical neuron types are obtained in a single circuit, through the adjustment of two biasing voltages, making the circuit suitable for applications in reconfigurable neuromorphic devices that implement biologically plausible spiking neural networks. ©2008 IEEE.

AB - This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 μm CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking and bursting firing patterns. The models of various cortical neuron types are obtained in a single circuit, through the adjustment of two biasing voltages, making the circuit suitable for applications in reconfigurable neuromorphic devices that implement biologically plausible spiking neural networks. ©2008 IEEE.

U2 - 10.1109/ISCAS.2008.4541785

DO - 10.1109/ISCAS.2008.4541785

M3 - Conference contribution

SN - 9781424416844

SP - 1784

EP - 1787

BT - Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst

T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008

Y2 - 1 July 2008

ER -

Integrated circuit implementation of a cortical neuron

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