Integrated circuit implementation of a cortical neuron

Jayawan H B Wijekoon, Piotr Dudek

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 μm CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking and bursting firing patterns. The models of various cortical neuron types are obtained in a single circuit, through the adjustment of two biasing voltages, making the circuit suitable for applications in reconfigurable neuromorphic devices that implement biologically plausible spiking neural networks. ©2008 IEEE.
    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst
    Pages1784-1787
    Number of pages3
    DOIs
    Publication statusPublished - 2008
    Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA
    Duration: 1 Jul 2008 → …

    Conference

    Conference2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
    CitySeattle, WA
    Period1/07/08 → …

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