Abstract
We present a dynamic voltage and frequency scaling technique within SoCs for per-core power management: the architecture allows for individual, self triggered performance-level scaling of the processing elements (PEs) within less than 100ns. This technique enables each core to adjust its local supply voltage and frequency depending on its current computational load. A test chip has been implemented in 28nm CMOS technology, as prototype of the SpiNNaker2 neuromorphic many core system, containing 4 PEs which are operational within the range of 1.1V down to 0.7V at frequencies from 666MHz down to 100MHz; The particular domain area of this application specific processor is real-time neuromorphics. Using a standard benchmark — the synfire chain — we show that the total power consumption can be reduced by 45%, with 85% baseline power reduction and a 30% reduction of energy per neuron and synapse computation, all while maintaining biological real-time operation.
Original language | English |
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DOIs | |
Publication status | Published - 2017 |
Event | IEEE International Symposium on Circuits and Systems: From Dreams to Innovation - Baltimore, United States Duration: 28 May 2017 → 31 May 2017 http://iscas2017.org/ |
Conference
Conference | IEEE International Symposium on Circuits and Systems |
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Abbreviated title | ISCAS 2017 |
Country/Territory | United States |
City | Baltimore |
Period | 28/05/17 → 31/05/17 |
Internet address |
Keywords
- MPSoC
- neuromorphic computing
- power management
- DVFS
- synfire chain