LLA: A low-latency asynchronous control with applications

Morteza Gholipour; Mehrdad Nourani; Doug Edwards; Ali Afzali-Kusha

doi:10.1109/ISSCS.2009.5206155

LLA: A low-latency asynchronous control with applications

Morteza Gholipour
, Mehrdad Nourani
, Doug Edwards
, Ali Afzali-Kusha

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we present a new low-latency asynchronous pipeline control circuit. The control circuit has only two gate delays in its critical path, which is faster compared to other works reported in the literature. Two applications of the design are shown to demonstrate its efficiency. The first is a 16-bit FIFOs and the second is a 4×4 multipliers which are designed both using LLA and GasP approaches. The designs are then simulated using HSPICE and 0.18μm CMOS technology parameters. The results show a latency improvement of about 38% in FIFOs and 18% in multipliers without any considerable degradation in other parameters such as power and throughput. The energy-delay curves also show better overall performance of LLA. © 2009 IEEE.

Original language	English
Title of host publication	2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009\|Int. Symp. Signals, Circuits Syst., ISSCS
Place of Publication	USA
Publisher	IEEE
ISBN (Print)	9781424437863
DOIs	https://doi.org/10.1109/ISSCS.2009.5206155
Publication status	Published - 2009
Event	2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009 - Iasi Duration: 1 Jul 2009 → …

Conference

Conference	2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009
City	Iasi
Period	1/07/09 → …

Keywords

CMOS integrated circuits , SPICE , asynchronous circuits , logic design , logic simulation , pipeline arithmetic

Access to Document

10.1109/ISSCS.2009.5206155

Cite this

@inproceedings{13baaa01f47d417081037129a10cef04,

title = "LLA: A low-latency asynchronous control with applications",

abstract = "In this paper, we present a new low-latency asynchronous pipeline control circuit. The control circuit has only two gate delays in its critical path, which is faster compared to other works reported in the literature. Two applications of the design are shown to demonstrate its efficiency. The first is a 16-bit FIFOs and the second is a 4×4 multipliers which are designed both using LLA and GasP approaches. The designs are then simulated using HSPICE and 0.18μm CMOS technology parameters. The results show a latency improvement of about 38\% in FIFOs and 18\% in multipliers without any considerable degradation in other parameters such as power and throughput. The energy-delay curves also show better overall performance of LLA. {\textcopyright} 2009 IEEE.",

keywords = "CMOS integrated circuits , SPICE , asynchronous circuits , logic design , logic simulation , pipeline arithmetic",

author = "Morteza Gholipour and Mehrdad Nourani and Doug Edwards and Ali Afzali-Kusha",

year = "2009",

doi = "10.1109/ISSCS.2009.5206155",

language = "English",

isbn = "9781424437863",

booktitle = "2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009|Int. Symp. Signals, Circuits Syst., ISSCS",

publisher = "IEEE",

address = "United States",

note = "2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009 ; Conference date: 01-07-2009",

}

Gholipour, M, Nourani, M, Edwards, D & Afzali-Kusha, A 2009, LLA: A low-latency asynchronous control with applications. in 2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009|Int. Symp. Signals, Circuits Syst., ISSCS. IEEE, USA, 2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009, Iasi, 1/07/09. https://doi.org/10.1109/ISSCS.2009.5206155

TY - GEN

T1 - LLA: A low-latency asynchronous control with applications

AU - Gholipour, Morteza

AU - Nourani, Mehrdad

AU - Edwards, Doug

AU - Afzali-Kusha, Ali

PY - 2009

Y1 - 2009

N2 - In this paper, we present a new low-latency asynchronous pipeline control circuit. The control circuit has only two gate delays in its critical path, which is faster compared to other works reported in the literature. Two applications of the design are shown to demonstrate its efficiency. The first is a 16-bit FIFOs and the second is a 4×4 multipliers which are designed both using LLA and GasP approaches. The designs are then simulated using HSPICE and 0.18μm CMOS technology parameters. The results show a latency improvement of about 38% in FIFOs and 18% in multipliers without any considerable degradation in other parameters such as power and throughput. The energy-delay curves also show better overall performance of LLA. © 2009 IEEE.

AB - In this paper, we present a new low-latency asynchronous pipeline control circuit. The control circuit has only two gate delays in its critical path, which is faster compared to other works reported in the literature. Two applications of the design are shown to demonstrate its efficiency. The first is a 16-bit FIFOs and the second is a 4×4 multipliers which are designed both using LLA and GasP approaches. The designs are then simulated using HSPICE and 0.18μm CMOS technology parameters. The results show a latency improvement of about 38% in FIFOs and 18% in multipliers without any considerable degradation in other parameters such as power and throughput. The energy-delay curves also show better overall performance of LLA. © 2009 IEEE.

KW - CMOS integrated circuits , SPICE , asynchronous circuits , logic design , logic simulation , pipeline arithmetic

U2 - 10.1109/ISSCS.2009.5206155

DO - 10.1109/ISSCS.2009.5206155

M3 - Conference contribution

SN - 9781424437863

BT - 2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009|Int. Symp. Signals, Circuits Syst., ISSCS

PB - IEEE

CY - USA

T2 - 2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009

Y2 - 1 July 2009

ER -

LLA: A low-latency asynchronous control with applications

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