Low-power clock distribution networks for 3-D ICs

Somayyeh Rahimian, Giovanni De Micheli, Vasilis F. Pavlidis

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing clock signal to the sink nodes. Test is another complex task for 3-D ICs, where pre-bond test is a prerequisite. This paper, consequently, introduces a design methodology for resonant 3-D clock networks that lowers the power of the clock networks while supporting pre-bond test. Several 3-D clock network topologies are explored in a 0.18 μm CMOS technology. Simulation results indicate 43% reduction in the power consumed by the resonant 3-D clock network as compared to a conventional buffered clock network. By properly distributing the inductance within the layers of the 3-D stack, resonance is ensured both in pre-bond test and normal operation. The important aspects of this approach are introduced in this paper.

    Original languageEnglish
    Title of host publication2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012
    DOIs
    Publication statusPublished - 2012
    Event2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012 - Eilat, Israel
    Duration: 14 Nov 201217 Nov 2012

    Conference

    Conference2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2012
    Country/TerritoryIsrael
    CityEilat
    Period14/11/1217/11/12

    Keywords

    • 3-D integration
    • clock distribution network
    • inductive link
    • resonant clocking
    • wireless testing

    Fingerprint

    Dive into the research topics of 'Low-power clock distribution networks for 3-D ICs'. Together they form a unique fingerprint.

    Cite this