Lowering power in an experimental RISC processor

Second year Computer Science students at the University of Manchester taking the VLSI Systems Design course complete the design of a 16-bit RISC processor down to silicon as the course laboratory exercise. Since the emphasis is on the design processes and testing, no especial effort is made to minimise power. This paper analyses the power dissipation of a typical pipelined design and then examines how the power efficiency might be improved at the architectural, RTL and logic levels. Simulation shows that the minimum dissipation is achieved by careful hand design; here, a factor of two improvement in the dissipation is achieved, with the major contribution being the logic level optimisation of the Register Bank to reduce the switching activity. © 2007 Elsevier B.V. All rights reserved.