Managing a massively-parallel resource-constrained computing architecture

Cameron Patterson; Thomas Preston; Francesco Galluppi; Steve Furber

doi:10.1109/DSD.2012.84

Managing a massively-parallel resource-constrained computing architecture

Cameron Patterson
, Thomas Preston
, Francesco Galluppi
, Steve Furber

Advanced Processor Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

One approach to creating a massively-parallel high-performance machine is to use large quantities of power-efficient processors, primarily due to the energy consumption of conventional high-performance computing designs. SpiNNaker is a novel high-performance architecture formed by large numbers of highly-interconnected low-power processing elements, more typically found in embedded systems. This paper presents the results of the implementation of a low-overhead management framework enabled by a universal translation layer: SpiNNmate. SpiNNmate is located between a SpiNNaker machine and the communication protocols of external applications, and we include results from a translation of the standards-based SNMP protocol to SpiNNaker. © 2012 IEEE.

Original language	English
Title of host publication	Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012\|Proc. - Euromicro Conf. Digit. Syst. Des., DSD
Pages	723-726
Number of pages	3
DOIs	https://doi.org/10.1109/DSD.2012.84
Publication status	Published - 2012
Event	15th Euromicro Conference on Digital System Design, DSD 2012 - Cesme, Izmir Duration: 1 Jul 2012 → …

Conference

Conference	15th Euromicro Conference on Digital System Design, DSD 2012
City	Cesme, Izmir
Period	1/07/12 → …

Keywords

Computer performance
Embedded
High performance computing
Middleboxes
Monitoring

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10.1109/DSD.2012.84

Cite this

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title = "Managing a massively-parallel resource-constrained computing architecture",

abstract = "One approach to creating a massively-parallel high-performance machine is to use large quantities of power-efficient processors, primarily due to the energy consumption of conventional high-performance computing designs. SpiNNaker is a novel high-performance architecture formed by large numbers of highly-interconnected low-power processing elements, more typically found in embedded systems. This paper presents the results of the implementation of a low-overhead management framework enabled by a universal translation layer: SpiNNmate. SpiNNmate is located between a SpiNNaker machine and the communication protocols of external applications, and we include results from a translation of the standards-based SNMP protocol to SpiNNaker. {\textcopyright} 2012 IEEE.",

keywords = "Computer performance, Embedded, High performance computing, Middleboxes, Monitoring",

author = "Cameron Patterson and Thomas Preston and Francesco Galluppi and Steve Furber",

year = "2012",

doi = "10.1109/DSD.2012.84",

language = "English",

isbn = "9780769547985",

pages = "723--726",

booktitle = "Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012|Proc. - Euromicro Conf. Digit. Syst. Des., DSD",

note = "15th Euromicro Conference on Digital System Design, DSD 2012 ; Conference date: 01-07-2012",

}

Patterson, C, Preston, T, Galluppi, F & Furber, S 2012, Managing a massively-parallel resource-constrained computing architecture. in Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012|Proc. - Euromicro Conf. Digit. Syst. Des., DSD. pp. 723-726, 15th Euromicro Conference on Digital System Design, DSD 2012, Cesme, Izmir, 1/07/12. https://doi.org/10.1109/DSD.2012.84

Managing a massively-parallel resource-constrained computing architecture. / Patterson, Cameron; Preston, Thomas; Galluppi, Francesco et al.
Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012|Proc. - Euromicro Conf. Digit. Syst. Des., DSD. 2012. p. 723-726.

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

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AU - Furber, Steve

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N2 - One approach to creating a massively-parallel high-performance machine is to use large quantities of power-efficient processors, primarily due to the energy consumption of conventional high-performance computing designs. SpiNNaker is a novel high-performance architecture formed by large numbers of highly-interconnected low-power processing elements, more typically found in embedded systems. This paper presents the results of the implementation of a low-overhead management framework enabled by a universal translation layer: SpiNNmate. SpiNNmate is located between a SpiNNaker machine and the communication protocols of external applications, and we include results from a translation of the standards-based SNMP protocol to SpiNNaker. © 2012 IEEE.

AB - One approach to creating a massively-parallel high-performance machine is to use large quantities of power-efficient processors, primarily due to the energy consumption of conventional high-performance computing designs. SpiNNaker is a novel high-performance architecture formed by large numbers of highly-interconnected low-power processing elements, more typically found in embedded systems. This paper presents the results of the implementation of a low-overhead management framework enabled by a universal translation layer: SpiNNmate. SpiNNmate is located between a SpiNNaker machine and the communication protocols of external applications, and we include results from a translation of the standards-based SNMP protocol to SpiNNaker. © 2012 IEEE.

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KW - Embedded

KW - High performance computing

KW - Middleboxes

KW - Monitoring

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Managing a massively-parallel resource-constrained computing architecture

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Keywords

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