TY - JOUR
T1 - MARBLE
T2 - An asynchronous on-chip macrocell bus
AU - Bainbridge, W. J.
AU - Furber, S. B.
PY - 2000/8/1
Y1 - 2000/8/1
N2 - This paper presents MARBLE, the Manchester Asynchronous Bus for Low Energy, a two channel asynchronous micropipeline-style VLSI macrocell bus. In addition to basic bus functions, MARBLE supports bus-bridging and test access, demonstrating that all the functions of a high speed macrocell bus can be implemented efficiently in a practical, fully asynchronous design style. MARBLE is used in the AMULET3i asynchronous Microprocessor system to connect the CPU core and DMA controller to RAM, ROM and peripherals. It exploits pipelining of the arbitration, address and data-cycles with a protocol based on split-transfers to meet the performance needs of such a system.
AB - This paper presents MARBLE, the Manchester Asynchronous Bus for Low Energy, a two channel asynchronous micropipeline-style VLSI macrocell bus. In addition to basic bus functions, MARBLE supports bus-bridging and test access, demonstrating that all the functions of a high speed macrocell bus can be implemented efficiently in a practical, fully asynchronous design style. MARBLE is used in the AMULET3i asynchronous Microprocessor system to connect the CPU core and DMA controller to RAM, ROM and peripherals. It exploits pipelining of the arbitration, address and data-cycles with a protocol based on split-transfers to meet the performance needs of such a system.
UR - http://www.scopus.com/inward/record.url?scp=0033724148&partnerID=8YFLogxK
U2 - 10.1016/S0141-9331(00)00075-2
DO - 10.1016/S0141-9331(00)00075-2
M3 - Article
AN - SCOPUS:0033724148
SN - 0141-9331
VL - 24
SP - 213
EP - 222
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
IS - 4
ER -