TY - CONF
T1 - Metal Stack and Partitioning Exploration for Monolithic 3D ICs
AU - Sketopoulos, Nikos
AU - Sotiriou, Christos
AU - Pavlidis, Vasilis
PY - 2020/5/11
Y1 - 2020/5/11
N2 - In this work, we investigate the effect of metal
stack and tier 3D IC partitioning methodologies on the Quality
of Results (QoR) of monolithic 3D circuits compared to their
2D counterparts. Two interconnect options are considered. For
the interconnect option, termed Single, a single metal stack is
used where cell pins lie on two lower metal layers. A Face
to Face (F2F) interconnect option is also considered where
cell pins lie on symmetrical lower and upper metal layers in
two different tiers. In addition, two 3D circuit partitioning
methodologies are investigated including the Greedy Bin-Based
Fidducia-Mattheyses (GBBFM) and a Displacement-based 3D Legaliser (3DLG). For both the 2D and 3D circuits, a multi-pass timing-driven In-Place Optimisation (IPO) is performed with an industrial P&R tool to extract the best QoR. For the 3D circuits, the IPO is applied after tier partitioning. The 45 nm nanoCAS library, a 3D library based on NANGATE 45 nm, is utilized and three typical benchmark circuits are analysed. The performance of 3D circuits is improved between 1% to 3%, total wirelength is significantly reduced, via usage is increased, yet the estimated power and cell area do not necessarily decrease. Single metal stack overall demonstrates better QoR than F2F integration.
AB - In this work, we investigate the effect of metal
stack and tier 3D IC partitioning methodologies on the Quality
of Results (QoR) of monolithic 3D circuits compared to their
2D counterparts. Two interconnect options are considered. For
the interconnect option, termed Single, a single metal stack is
used where cell pins lie on two lower metal layers. A Face
to Face (F2F) interconnect option is also considered where
cell pins lie on symmetrical lower and upper metal layers in
two different tiers. In addition, two 3D circuit partitioning
methodologies are investigated including the Greedy Bin-Based
Fidducia-Mattheyses (GBBFM) and a Displacement-based 3D Legaliser (3DLG). For both the 2D and 3D circuits, a multi-pass timing-driven In-Place Optimisation (IPO) is performed with an industrial P&R tool to extract the best QoR. For the 3D circuits, the IPO is applied after tier partitioning. The 45 nm nanoCAS library, a 3D library based on NANGATE 45 nm, is utilized and three typical benchmark circuits are analysed. The performance of 3D circuits is improved between 1% to 3%, total wirelength is significantly reduced, via usage is increased, yet the estimated power and cell area do not necessarily decrease. Single metal stack overall demonstrates better QoR than F2F integration.
M3 - Poster
ER -