Abstract
As the demand for low power electronic products continues to increase there is a need for the designers of CMOS circuits to find ways to reduce the power consumption of their circuits. This paper introduces a practical approach to improve power-efficiency based upon the analysis of a breakdown of the power consumption of an existing design. The breakdown is used to identify the most promising subcircuits for improvement. A 32 × 32 asynchronous pipelined integer multiplier is used as a case-study. Following the proposed methodology, the redesigned multiplier uses less than 40% of the energy per instruction of its predecessor. An asynchronous latch controller is also proposed which is smaller and faster than previous 4-phase fully-decoupled latch controllers. © Springer-Verlag 2004.
| Original language | English |
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| Title of host publication | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)|Lect. Notes Comput. Sci. |
| Publisher | Springer Nature |
| Pages | 289-300 |
| Number of pages | 11 |
| Volume | 3254 |
| Publication status | Published - 2004 |
| Event | Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings - Duration: 1 Jan 1824 → … http://dblp.uni-trier.de/db/conf/patmos/patmos2004.html#LiuF04http://dblp.uni-trier.de/rec/bibtex/conf/patmos/LiuF04.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/patmos/LiuF04 |
Publication series
| Name | Lecture Notes in Computer Science |
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Conference
| Conference | Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings |
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| Period | 1/01/24 → … |
| Internet address |