Abstract
Cryptographic circuits are sensitive to electromagnetic (EM) side-channel attacks (SCAs), which aim to detect the EM emissions of these circuits. A novel technique is proposed to mitigate such attacks, by reducing the correlation between the processed data and EM emissions. This objective is achieved by combining energy-efficient data inversion with dynamic delay insertion. The added delay enhances the immunity against EM attacks for the cryptographic circuit without performance degradation and, in specific scenarios, even improves performance.
Simulation results on a set of EM traces, captured from an 8-bit interposer-based off-chip memory bus, demonstrate the efficiency of the proposed technique by decreasing SNR below 1 and improving the worst-case bus latency by 9.5%.
Simulation results on a set of EM traces, captured from an 8-bit interposer-based off-chip memory bus, demonstrate the efficiency of the proposed technique by decreasing SNR below 1 and improving the worst-case bus latency by 9.5%.
Original language | English |
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Publication status | Accepted/In press - 15 Jan 2022 |
Event | IEEE International Symposium on Circuits and Systems - Austin, United States Duration: 28 May 2022 → 1 Jun 2022 https://www.iscas2022.org/ |
Conference
Conference | IEEE International Symposium on Circuits and Systems |
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Abbreviated title | ISCAS |
Country/Territory | United States |
City | Austin |
Period | 28/05/22 → 1/06/22 |
Internet address |