Abstract
A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31μm pitch. Each processor element includes 14 bits of digital memory in addition to 7 analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ∼1μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18μm CMOS technology. © 2012 IEEE.
Original language | English |
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Title of host publication | 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012|IEEE Int. Conf. Electron., Circuits, Syst., ICECS |
Pages | 324-327 |
Number of pages | 3 |
DOIs | |
Publication status | Published - 2012 |
Event | 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 - Seville, Seville Duration: 1 Jul 2012 → … |
Conference
Conference | 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 |
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City | Seville, Seville |
Period | 1/07/12 → … |
Keywords
- asynchronous image processing
- cellular processor
- smart sensor
- Vision chip