MLP-aware instruction queue resizing: the key to power-efficient performance

Pavlos Petoumenos, Georgia Psychou, Stefanos Kaxiras, Juan Manuel Cebrian Gonzalez, Juan Luis Aragon

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


Several techniques aiming to improve power-efficiency (measured as EDP) in out-of-order cores trade energy with performance. Prime examples are the techniques to resize the instruction queue (IQ). While most of them produce good results, they fail to take into account that changing the timing of memory accesses can have significant consequences on the memory-level parallelism (MLP) of the application and thus incur disproportional performance degradation. We propose a novel mechanism that deals with this realization by collecting fine-grain information about the maximum IQ resizing that does not affect the MLP of the program. This information is used to override the resizing enforced by feedback mechanisms when this resizing might reduce MLP. We compare our technique to a previously proposed non-MLP-aware management technique and our results show a significant increase in EDP savings for most benchmarks of the SPEC2000 suite.
Original languageEnglish
Title of host publicationArchitecture of computing systems - ARCS 2010
Subtitle of host publication23rd international conference Hannover, Germany, February 22-25, 2010 proceedings
EditorsChristian Müller-Schloer, Wolfgang Karl, Sami Yehia
Place of PublicationBerlin, Heidelberg, New York
PublisherSpringer Nature
Number of pages13
ISBN (Electronic)9783642119507
ISBN (Print)9783642119491
Publication statusPublished - 1 Dec 2010
Event23rd International Conference on Architecture of Computing Systems - Hannover, Germany
Duration: 22 Feb 201025 Feb 2010

Publication series

NameLecture Notes in Computer Science
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Conference23rd International Conference on Architecture of Computing Systems
Abbreviated titleARCS 2010


  • Execution Time
  • Basic Block
  • Computer Architecture
  • Cache Size
  • Instruction Stream


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