TY - JOUR
T1 - MU6-G. A new design to achieve mainframe performance from a mini-sized computer
AU - Edwards, D. B.G.
AU - Knowles, A. E.
AU - Woods, J. V.
PY - 1980/5/6
Y1 - 1980/5/6
N2 - MU6-G is a high performance machine useful for general or scientific applications. Its order code and architecture are designed to be sympathetic to the needs of the operating system and to both the compilation and execution of programs written in high level languages and to support a word size suitable for high precision scientific computations. Advanced technology, coupled with simplicity of design, is used to achieve a high and more readily predictable performance. Innovative features include the unique organisation of the virtual memory mapping hardware and the use of a combined operand and instruction buffer-store, accessed using virtual addresses. Fault diagnosis is aided by the inclusion of a microprocessor based diagnostic controller which has read/write access to all bistable devices in the machine and has control of the system clock. The paper includes a description of the various functional units and gives estimates of expected performance.
AB - MU6-G is a high performance machine useful for general or scientific applications. Its order code and architecture are designed to be sympathetic to the needs of the operating system and to both the compilation and execution of programs written in high level languages and to support a word size suitable for high precision scientific computations. Advanced technology, coupled with simplicity of design, is used to achieve a high and more readily predictable performance. Innovative features include the unique organisation of the virtual memory mapping hardware and the use of a combined operand and instruction buffer-store, accessed using virtual addresses. Fault diagnosis is aided by the inclusion of a microprocessor based diagnostic controller which has read/write access to all bistable devices in the machine and has control of the system clock. The paper includes a description of the various functional units and gives estimates of expected performance.
UR - http://www.scopus.com/inward/record.url?scp=84939706930&partnerID=8YFLogxK
U2 - 10.1145/800053.801921
DO - 10.1145/800053.801921
M3 - Conference article
AN - SCOPUS:84939706930
SN - 1063-6897
SP - 161
EP - 167
JO - Proceedings - International Symposium on Computer Architecture
JF - Proceedings - International Symposium on Computer Architecture
T2 - 7th Annual Symposium on Computer Architecture
Y2 - 6 May 1980 through 8 May 1980
ER -