Abstract
This paper proposes a new microprocessor architecture that achieves high performance through the use of a large number of registers arranged in a novel fashion. The power of the architecture has been assessed using benchmark programs, and it appears that the code can rival stacking machine code for compactness, while having the potential to run faster than any conventional architecture.
| Original language | English |
|---|---|
| Pages (from-to) | 208-217 |
| Number of pages | 10 |
| Journal | Computer Journal |
| Volume | 26 |
| Issue number | 3 |
| Publication status | Published - Aug 1983 |