No-handshake asynchronous survivor memory unit for a Viterbi decoder

Wei Shao; Linda Brackenbury

doi:10.1109/ICECS.2007.4511095

No-handshake asynchronous survivor memory unit for a Viterbi decoder

Wei Shao, Linda Brackenbury

Research output: Chapter in Book/Conference proceeding › Conference contribution

Abstract

The Survivor Memory Unit (SMU) is a vital part of a Viterbi decoder design. So far, classical implementations of SMU employ the register exchange or the trace back approaches. In the conventional trace back implementation, a read-write RAM architecture is generally adopted which requires a large size of memory. This gives the SMU design both area and power overhead. This paper presents a new no-handshake asynchronous approach to implement the trace back method. The SMU design based on this new architecture is a mixed synchronous and asynchronous circuit. Post-layout simulation results on a 18μm process show the new architecture saves more than 84% of the power dissipated compare with a synchronised SMU design using a low power logic family and 30% compared with a handshaking asynchronous design. ©2007 IEEE.

Original language	English
Title of host publication	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems\|Proc IEEE Int Conf Electron Circuits Syst
Publisher	IEEE
Pages	729-734
Number of pages	5
ISBN (Print)	1424413788, 9781424413782
DOIs	https://doi.org/10.1109/ICECS.2007.4511095
Publication status	Published - 2007
Event	14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech Duration: 1 Jul 2007 → …

Conference

Conference	14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
City	Marrakech
Period	1/07/07 → …

Keywords

Engineering, Electrical & Electronic

Access to Document

10.1109/ICECS.2007.4511095

Cite this

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title = "No-handshake asynchronous survivor memory unit for a Viterbi decoder",

abstract = "The Survivor Memory Unit (SMU) is a vital part of a Viterbi decoder design. So far, classical implementations of SMU employ the register exchange or the trace back approaches. In the conventional trace back implementation, a read-write RAM architecture is generally adopted which requires a large size of memory. This gives the SMU design both area and power overhead. This paper presents a new no-handshake asynchronous approach to implement the trace back method. The SMU design based on this new architecture is a mixed synchronous and asynchronous circuit. Post-layout simulation results on a 18μm process show the new architecture saves more than 84% of the power dissipated compare with a synchronised SMU design using a low power logic family and 30% compared with a handshaking asynchronous design. {\textcopyright}2007 IEEE.",

keywords = "Engineering, Electrical & Electronic",

author = "Wei Shao and Linda Brackenbury",

note = "Ieee Shao, Wei Brackenbury, Linda 6 NEW YORK BHP05; 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 ; Conference date: 01-07-2007",

year = "2007",

doi = "10.1109/ICECS.2007.4511095",

language = "English",

isbn = "1424413788",

pages = "729--734",

booktitle = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems|Proc IEEE Int Conf Electron Circuits Syst",

publisher = "IEEE",

address = "United States",

}

Shao, W & Brackenbury, L 2007, No-handshake asynchronous survivor memory unit for a Viterbi decoder. in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems|Proc IEEE Int Conf Electron Circuits Syst. IEEE, pp. 729-734, 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007, Marrakech, 1/07/07. https://doi.org/10.1109/ICECS.2007.4511095

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AU - Brackenbury, Linda

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PY - 2007

Y1 - 2007

N2 - The Survivor Memory Unit (SMU) is a vital part of a Viterbi decoder design. So far, classical implementations of SMU employ the register exchange or the trace back approaches. In the conventional trace back implementation, a read-write RAM architecture is generally adopted which requires a large size of memory. This gives the SMU design both area and power overhead. This paper presents a new no-handshake asynchronous approach to implement the trace back method. The SMU design based on this new architecture is a mixed synchronous and asynchronous circuit. Post-layout simulation results on a 18μm process show the new architecture saves more than 84% of the power dissipated compare with a synchronised SMU design using a low power logic family and 30% compared with a handshaking asynchronous design. ©2007 IEEE.

AB - The Survivor Memory Unit (SMU) is a vital part of a Viterbi decoder design. So far, classical implementations of SMU employ the register exchange or the trace back approaches. In the conventional trace back implementation, a read-write RAM architecture is generally adopted which requires a large size of memory. This gives the SMU design both area and power overhead. This paper presents a new no-handshake asynchronous approach to implement the trace back method. The SMU design based on this new architecture is a mixed synchronous and asynchronous circuit. Post-layout simulation results on a 18μm process show the new architecture saves more than 84% of the power dissipated compare with a synchronised SMU design using a low power logic family and 30% compared with a handshaking asynchronous design. ©2007 IEEE.

KW - Engineering, Electrical & Electronic

U2 - 10.1109/ICECS.2007.4511095

DO - 10.1109/ICECS.2007.4511095

M3 - Conference contribution

SN - 1424413788

SN - 9781424413782

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EP - 734

BT - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems|Proc IEEE Int Conf Electron Circuits Syst

PB - IEEE

T2 - 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007

Y2 - 1 July 2007

ER -

No-handshake asynchronous survivor memory unit for a Viterbi decoder

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