Optimal connectivity in hardware-targetted MLP networks

A. D. Rast, S. Welbourne, X. Jin, S. B. Furber

Research output: Chapter in Book/Conference proceedingConference contributionpeer-review

Abstract

In large neural networks, partial connectivity is both biologically plausible and a matter of necessity when targetting a hardware implementation. We are using the SpiNNaker neural chip multiprocessor to model such networks as a drop-in replacement for the Lens network simulator. For the popular MLP network, a theoretical model of the relation between connectivity, network size and gain in the activation function provides a method to set these parameters to near-optimal values. Using the model, we run a series of network simulations in Lens, permuting the parameters to explore the effects in 2 networks of different size and application. Initial test results show a clear connectivity-gain relation and a benefit to partial connectivity in both networks, with optimal hidden-output connectivity values ranging from ∼10%-∼30% depending on the network type. We show that optimal connectivity-gain settings reduce training time, minimising error oscillations during learning. Preliminary analysis also suggests that while very low connectivities may improve error they may also result in decreased adaptivity to new inputs or component failure. These results in combination with the theoretical relation give a method for determining reasonable initial connectivity and gain values at design time for an MLP network, allowing more efficient use of hardware resources such as SpiNNaker and faster simulations in any software environment. They also suggest a different way of considering the problem of MLP network design: rather than specify a fixed number of neurons, specify a fixed number of connections and vary the number of neurons to reach optimal connectivity. © 2009 IEEE.
Original languageEnglish
Title of host publicationProceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks
Place of PublicationUSA
PublisherIEEE
Pages2619-2626
Number of pages7
ISBN (Print)9781424435531
DOIs
Publication statusPublished - 2009
Event2009 International Joint Conference on Neural Networks, IJCNN 2009 - Atlanta, GA
Duration: 1 Jul 2009 → …

Conference

Conference2009 International Joint Conference on Neural Networks, IJCNN 2009
CityAtlanta, GA
Period1/07/09 → …

Keywords

  • microprocessor chips
  • multilayer perceptrons

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