Abstract
A 'natural' way of describing an algorithm is as a data flow. When synthesizing hardware a lot of design effort can be expended on details of mapping this into clock cycles. However there are several good reasons - not least the maturity of Electronic Design Automation (EDA) tools - for implementing circuits synchronously. This paper describes: a) an approach to transform an asynchronous dataflow network into a synchronous elastic implementation whilst retaining the characteristic, relatively free, flow of data. b) work to translate a synchronous elastic dataflow into a synchronous circuit whose deterministic properties pave the road for further behavioural analysis of the system. The results exhibit considerable benefit in terms of area over an asynchronous dataflow realisation.
Original language | English |
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Title of host publication | Digital System Design (DSD), 2014 17th Euromicro Conference on |
Place of Publication | USA |
Publisher | IEE |
Pages | 604-617 |
Number of pages | 14 |
DOIs | |
Publication status | Published - 27 Aug 2014 |
Event | Euromicro Conference on Digital System Design (DSD) - Verona, Italy Duration: 27 Aug 2014 → 29 Aug 2014 |
Conference
Conference | Euromicro Conference on Digital System Design (DSD) |
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City | Verona, Italy |
Period | 27/08/14 → 29/08/14 |
Keywords
- data flow analysis;electronic design automation;EDA tools;asynchronous dataflow network;asynchronous dataflow realisation;asynchronous elastic dataflows;behavioural analysis;clock cycles;data flow;electronic design automation tools;hardware;leveraging clocked EDA;optimised synthesis;synchronous circuit;synchronous elastic implementation;Clocks;Concurrent computing;Elasticity;Protocols;Synchronization;System-on-chip;Asynchronous Dataflow;CAD tools;Synchronous Elastic Systems;Teak Dataflow Networks