Placing partially reconfigurable stream processing applications on FPGAs

Dirk Koch; Peter Cheung; Wayne Luk; Christina Silvano

doi:10.1109/FPL.2015.7294001

Placing partially reconfigurable stream processing applications on FPGAs

Dirk Koch, Peter Cheung (Editor), Wayne Luk (Editor), Christina Silvano (Editor)

Advanced Processor Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

Finding placement locations for modules on an FPGA in a limited amount of time is a crucial task that determines the efficiency of a dynamic partially reconfigurable system. In this work, we will define a placement method based on transforming the inherent two dimensional (2D) structure of the FPGA into a one dimensional string and employing string matching. Moreover, our model is suited to compute a module placement over multiple chained reconfigurable regions. Our algorithm is based on a hybrid approach consisting of an offline precompute phase at design-time which in turn is used to speed-up module placement at run-time.

Original language	English
Title of host publication	Prooceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL 2015)
Editors	Peter Cheung, Wayne Luk, Christina Silvano
Publisher	IEEE
Pages	1-4
Number of pages	4
DOIs	https://doi.org/10.1109/FPL.2015.7294001
Publication status	Published - 2 Sept 2015
Event	International Conference on Field Programmable Logic and Applications (FPL) - London Duration: 2 Sept 2015 → 4 Sept 2015

Conference

Conference	International Conference on Field Programmable Logic and Applications (FPL)
City	London
Period	2/09/15 → 4/09/15

Keywords

FPGA
module placement
reconfiguration

Access to Document

10.1109/FPL.2015.7294001

Cite this

@inproceedings{61eee6a0aa3a4f3f9864234a5bd5369b,

title = "Placing partially reconfigurable stream processing applications on FPGAs",

abstract = "Finding placement locations for modules on an FPGA in a limited amount of time is a crucial task that determines the efficiency of a dynamic partially reconfigurable system. In this work, we will define a placement method based on transforming the inherent two dimensional (2D) structure of the FPGA into a one dimensional string and employing string matching. Moreover, our model is suited to compute a module placement over multiple chained reconfigurable regions. Our algorithm is based on a hybrid approach consisting of an offline precompute phase at design-time which in turn is used to speed-up module placement at run-time.",

keywords = "FPGA, module placement, reconfiguration",

author = "Dirk Koch and Peter Cheung and Wayne Luk and Christina Silvano",

note = "The research leading to these results has received funding from the European Union{\textquoteright}s 7th Framework Programme (FP7/2007-2013) under grant agreement 318633 (AXLE project http://axleproject.eu/).; International Conference on Field Programmable Logic and Applications (FPL) ; Conference date: 02-09-2015 Through 04-09-2015",

year = "2015",

month = sep,

day = "2",

doi = "10.1109/FPL.2015.7294001",

language = "English",

pages = "1--4",

editor = "Peter Cheung and Wayne Luk and Christina Silvano",

booktitle = "Prooceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL 2015)",

publisher = "IEEE",

address = "United States",

}

Koch, D, Cheung, P (ed.), Luk, W (ed.) & Silvano, C (ed.) 2015, Placing partially reconfigurable stream processing applications on FPGAs. in P Cheung, W Luk & C Silvano (eds), Prooceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL 2015). IEEE, pp. 1-4, International Conference on Field Programmable Logic and Applications (FPL), London, 2/09/15. https://doi.org/10.1109/FPL.2015.7294001

Placing partially reconfigurable stream processing applications on FPGAs. / Koch, Dirk; Cheung, Peter (Editor); Luk, Wayne (Editor) et al.
Prooceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL 2015). ed. / Peter Cheung; Wayne Luk; Christina Silvano. IEEE, 2015. p. 1-4.

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Placing partially reconfigurable stream processing applications on FPGAs

AU - Koch, Dirk

A2 - Cheung, Peter

A2 - Luk, Wayne

A2 - Silvano, Christina

A2 - Cheung, Peter

A2 - Luk, Wayne

A2 - Silvano, Christina

N1 - The research leading to these results has received funding from the European Union’s 7th Framework Programme (FP7/2007-2013) under grant agreement 318633 (AXLE project http://axleproject.eu/).

PY - 2015/9/2

Y1 - 2015/9/2

N2 - Finding placement locations for modules on an FPGA in a limited amount of time is a crucial task that determines the efficiency of a dynamic partially reconfigurable system. In this work, we will define a placement method based on transforming the inherent two dimensional (2D) structure of the FPGA into a one dimensional string and employing string matching. Moreover, our model is suited to compute a module placement over multiple chained reconfigurable regions. Our algorithm is based on a hybrid approach consisting of an offline precompute phase at design-time which in turn is used to speed-up module placement at run-time.

AB - Finding placement locations for modules on an FPGA in a limited amount of time is a crucial task that determines the efficiency of a dynamic partially reconfigurable system. In this work, we will define a placement method based on transforming the inherent two dimensional (2D) structure of the FPGA into a one dimensional string and employing string matching. Moreover, our model is suited to compute a module placement over multiple chained reconfigurable regions. Our algorithm is based on a hybrid approach consisting of an offline precompute phase at design-time which in turn is used to speed-up module placement at run-time.

KW - FPGA

KW - module placement

KW - reconfiguration

U2 - 10.1109/FPL.2015.7294001

DO - 10.1109/FPL.2015.7294001

M3 - Conference contribution

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EP - 4

BT - Prooceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL 2015)

PB - IEEE

T2 - International Conference on Field Programmable Logic and Applications (FPL)

Y2 - 2 September 2015 through 4 September 2015

ER -

Placing partially reconfigurable stream processing applications on FPGAs

Abstract

Conference

Keywords

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Cite this