Power control within a coherent multi-processing system

Anthony Goodacre (Other), Julie-Anne Pruvost (Other), Frederic Piry (Other), Norbert Lataille (Other), Gilles Grandou (Other)

Research output: Patent


Within a multi-processing system including a plurality of processor cores 4, 6 operating in accordance with coherent multi-processing, each of the cores includes a cache memory 10, 12 storing local copies of data values from a coherent memory region. The respective processor cores may be placed into a power saving mode in which they are non-operative whilst the cache memory remains responsive to coherency management requests such that the system as a whole can continue to operate and manage coherency.
Original languageEnglish
Publication statusPublished - 30 Mar 2004


Dive into the research topics of 'Power control within a coherent multi-processing system'. Together they form a unique fingerprint.

Cite this