Power control within a coherent multi-processing system

Anthony Goodacre; Julie-Anne Pruvost; Frederic Piry; Norbert Lataille; Gilles Grandou

Power control within a coherent multi-processing system

Anthony Goodacre (Other), Julie-Anne Pruvost (Other), Frederic Piry (Other), Norbert Lataille (Other), Gilles Grandou (Other)

Advanced Processor Technology

Research output: Patent

Abstract

Within a multi-processing system including a plurality of processor cores 4, 6 operating in accordance with coherent multi-processing, each of the cores includes a cache memory 10, 12 storing local copies of data values from a coherent memory region. The respective processor cores may be placed into a power saving mode in which they are non-operative whilst the cache memory remains responsive to coherency management requests such that the system as a whole can continue to operate and manage coherency.

Original language	English
Publication status	Published - 30 Mar 2004

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title = "Power control within a coherent multi-processing system",

abstract = "Within a multi-processing system including a plurality of processor cores 4, 6 operating in accordance with coherent multi-processing, each of the cores includes a cache memory 10, 12 storing local copies of data values from a coherent memory region. The respective processor cores may be placed into a power saving mode in which they are non-operative whilst the cache memory remains responsive to coherency management requests such that the system as a whole can continue to operate and manage coherency.",

author = "Anthony Goodacre and Julie-Anne Pruvost and Frederic Piry and Norbert Lataille and Gilles Grandou",

year = "2004",

month = mar,

day = "30",

language = "English",

type = "Patent",

}

TY - PAT

T1 - Power control within a coherent multi-processing system

A2 - Goodacre, Anthony

A2 - Pruvost, Julie-Anne

A2 - Piry, Frederic

A2 - Lataille, Norbert

A2 - Grandou, Gilles

N1 - Application number: 10/812,050Location issued: US

PY - 2004/3/30

Y1 - 2004/3/30

N2 - Within a multi-processing system including a plurality of processor cores 4, 6 operating in accordance with coherent multi-processing, each of the cores includes a cache memory 10, 12 storing local copies of data values from a coherent memory region. The respective processor cores may be placed into a power saving mode in which they are non-operative whilst the cache memory remains responsive to coherency management requests such that the system as a whole can continue to operate and manage coherency.

AB - Within a multi-processing system including a plurality of processor cores 4, 6 operating in accordance with coherent multi-processing, each of the cores includes a cache memory 10, 12 storing local copies of data values from a coherent memory region. The respective processor cores may be placed into a power saving mode in which they are non-operative whilst the cache memory remains responsive to coherency management requests such that the system as a whole can continue to operate and manage coherency.

M3 - Patent

ER -

Power control within a coherent multi-processing system

Abstract

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