Power, delay and area efficient self-timed multiplexer and demultiplexer designs

P. Balasubramanian; D. A. Edwards

doi:10.1109/DTIS.2009.4938050

Power, delay and area efficient self-timed multiplexer and demultiplexer designs

P. Balasubramanian, D. A. Edwards

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Efficient gate level design methods for robust selftimed realization of arbitrary size multiplexer and demultiplexer function blocks, using elements of a commercial standard cell library are discussed in this paper. While the optimal self-timed multiplexer implementations correspond to strong-indication, the optimal self-timed demultiplexer implementations pertain to weak-indication phenomenon. The design methods presented are scalable and enable achieving simultaneous optimization in power, delay and area parameters.

Original language	English
Title of host publication	Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era\|Proc. DTIS - IEEE Int. Conf. Des. Technol. Integr. Syst. Nanoscale Era
Place of Publication	USA
Publisher	IEEE
Pages	173-178
Number of pages	5
ISBN (Print)	9781424443215
DOIs	https://doi.org/10.1109/DTIS.2009.4938050
Publication status	Published - 2009
Event	2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'09 - Cairo Duration: 1 Jul 2009 → …

Conference

Conference	2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'09
City	Cairo
Period	1/07/09 → …

Keywords

decision circuits , demultiplexing equipment , logic design , multiplexing equipment

Access to Document

10.1109/DTIS.2009.4938050

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Balasubramanian, P., & Edwards, D. A. (2009). Power, delay and area efficient self-timed multiplexer and demultiplexer designs. In Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era|Proc. DTIS - IEEE Int. Conf. Des. Technol. Integr. Syst. Nanoscale Era (pp. 173-178). IEEE. https://doi.org/10.1109/DTIS.2009.4938050

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title = "Power, delay and area efficient self-timed multiplexer and demultiplexer designs",

abstract = "Efficient gate level design methods for robust selftimed realization of arbitrary size multiplexer and demultiplexer function blocks, using elements of a commercial standard cell library are discussed in this paper. While the optimal self-timed multiplexer implementations correspond to strong-indication, the optimal self-timed demultiplexer implementations pertain to weak-indication phenomenon. The design methods presented are scalable and enable achieving simultaneous optimization in power, delay and area parameters.",

keywords = "decision circuits , demultiplexing equipment , logic design , multiplexing equipment",

author = "P. Balasubramanian and Edwards, {D. A.}",

year = "2009",

doi = "10.1109/DTIS.2009.4938050",

language = "English",

isbn = "9781424443215",

pages = "173--178",

booktitle = "Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era|Proc. DTIS - IEEE Int. Conf. Des. Technol. Integr. Syst. Nanoscale Era",

publisher = "IEEE",

address = "United States",

note = "2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'09 ; Conference date: 01-07-2009",

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Balasubramanian, P & Edwards, DA 2009, Power, delay and area efficient self-timed multiplexer and demultiplexer designs. in Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era|Proc. DTIS - IEEE Int. Conf. Des. Technol. Integr. Syst. Nanoscale Era. IEEE, USA, pp. 173-178, 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'09, Cairo, 1/07/09. https://doi.org/10.1109/DTIS.2009.4938050

Power, delay and area efficient self-timed multiplexer and demultiplexer designs. / Balasubramanian, P.; Edwards, D. A.
Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era|Proc. DTIS - IEEE Int. Conf. Des. Technol. Integr. Syst. Nanoscale Era. USA: IEEE, 2009. p. 173-178.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Edwards, D. A.

PY - 2009

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N2 - Efficient gate level design methods for robust selftimed realization of arbitrary size multiplexer and demultiplexer function blocks, using elements of a commercial standard cell library are discussed in this paper. While the optimal self-timed multiplexer implementations correspond to strong-indication, the optimal self-timed demultiplexer implementations pertain to weak-indication phenomenon. The design methods presented are scalable and enable achieving simultaneous optimization in power, delay and area parameters.

AB - Efficient gate level design methods for robust selftimed realization of arbitrary size multiplexer and demultiplexer function blocks, using elements of a commercial standard cell library are discussed in this paper. While the optimal self-timed multiplexer implementations correspond to strong-indication, the optimal self-timed demultiplexer implementations pertain to weak-indication phenomenon. The design methods presented are scalable and enable achieving simultaneous optimization in power, delay and area parameters.

KW - decision circuits , demultiplexing equipment , logic design , multiplexing equipment

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DO - 10.1109/DTIS.2009.4938050

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BT - Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era|Proc. DTIS - IEEE Int. Conf. Des. Technol. Integr. Syst. Nanoscale Era

PB - IEEE

CY - USA

T2 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS'09

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Balasubramanian P, Edwards DA. Power, delay and area efficient self-timed multiplexer and demultiplexer designs. In Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era|Proc. DTIS - IEEE Int. Conf. Des. Technol. Integr. Syst. Nanoscale Era. USA: IEEE. 2009. p. 173-178 doi: 10.1109/DTIS.2009.4938050

Power, delay and area efficient self-timed multiplexer and demultiplexer designs

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